From 7a4db1da2641c785f5fd9d2365df2a213f3aaade Mon Sep 17 00:00:00 2001
From: Lachezar Lechev <elpiel93@gmail.com>
Date: Mon, 20 Mar 2023 16:34:30 +0200
Subject: [PATCH] fix(rp): spi transfer

Signed-off-by: Lachezar Lechev <elpiel93@gmail.com>
---
 embassy-rp/src/dma.rs |  1 +
 embassy-rp/src/spi.rs | 46 +++++++++++++++++++++++++++++++++++++------
 2 files changed, 41 insertions(+), 6 deletions(-)

diff --git a/embassy-rp/src/dma.rs b/embassy-rp/src/dma.rs
index 05adcecd..ba07a88d 100644
--- a/embassy-rp/src/dma.rs
+++ b/embassy-rp/src/dma.rs
@@ -1,3 +1,4 @@
+//! Direct Memory Access (DMA)
 use core::future::Future;
 use core::pin::Pin;
 use core::sync::atomic::{compiler_fence, Ordering};
diff --git a/embassy-rp/src/spi.rs b/embassy-rp/src/spi.rs
index 584370d5..c48e33fc 100644
--- a/embassy-rp/src/spi.rs
+++ b/embassy-rp/src/spi.rs
@@ -1,3 +1,4 @@
+//! Serial Peripheral Interface
 use core::marker::PhantomData;
 
 use embassy_embedded_hal::SetConfig;
@@ -385,19 +386,36 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
     async fn transfer_inner(&mut self, rx_ptr: *mut [u8], tx_ptr: *const [u8]) -> Result<(), Error> {
         let (_, from_len) = crate::dma::slice_ptr_parts(tx_ptr);
         let (_, to_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
-        assert_eq!(from_len, to_len);
+
         unsafe {
             self.inner.regs().dmacr().write(|reg| {
                 reg.set_rxdmae(true);
                 reg.set_txdmae(true);
             })
         };
-        let tx_ch = self.tx_dma.as_mut().unwrap();
-        let tx_transfer = unsafe {
-            // If we don't assign future to a variable, the data register pointer
-            // is held across an await and makes the future non-Send.
-            crate::dma::write(tx_ch, tx_ptr, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
+
+        let mut tx_ch = self.tx_dma.as_mut().unwrap();
+        // If we don't assign future to a variable, the data register pointer
+        // is held across an await and makes the future non-Send.
+        let tx_transfer = async {
+            let p = self.inner.regs();
+            unsafe {
+                crate::dma::write(&mut tx_ch, tx_ptr, p.dr().ptr() as *mut _, T::TX_DREQ).await;
+
+                if from_len > to_len {
+                    let write_bytes_len = from_len - to_len;
+                    // disable incrementation of buffer
+                    tx_ch.regs().ctrl_trig().modify(|ctrl_trig| {
+                        ctrl_trig.set_incr_write(false);
+                        ctrl_trig.set_incr_read(false);
+                    });
+
+                    // write dummy data
+                    crate::dma::write_repeated(tx_ch, p.dr().ptr() as *mut u8, write_bytes_len, T::TX_DREQ).await
+                }
+            }
         };
+
         let rx_ch = self.rx_dma.as_mut().unwrap();
         let rx_transfer = unsafe {
             // If we don't assign future to a variable, the data register pointer
@@ -405,6 +423,22 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
             crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, rx_ptr, T::RX_DREQ)
         };
         join(tx_transfer, rx_transfer).await;
+
+        // if tx > rx we should clear any overflow of the FIFO SPI buffer
+        if from_len > to_len {
+            let p = self.inner.regs();
+            unsafe {
+                while p.sr().read().bsy() {}
+
+                // clear RX FIFO contents to prevent stale reads
+                while p.sr().read().rne() {
+                    let _: u16 = p.dr().read().data();
+                }
+                // clear RX overrun interrupt
+                p.icr().write(|w| w.set_roric(true));
+            }
+        }
+
         Ok(())
     }
 }