rp/uart: use lockfree ringbuffer.
This gets rid of another PeripheralMutex usage.
This commit is contained in:
@ -7,6 +7,11 @@ use crate::gpio::sealed::Pin;
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use crate::gpio::AnyPin;
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use crate::{pac, peripherals, Peripheral};
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#[cfg(feature = "nightly")]
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mod buffered;
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#[cfg(feature = "nightly")]
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pub use buffered::{BufferedUart, BufferedUartRx, BufferedUartTx};
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum DataBits {
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DataBits5,
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@ -196,7 +201,7 @@ impl<'d, T: Instance> Uart<'d, T, Blocking> {
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config: Config,
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) -> Self {
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into_ref!(tx, rx);
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Self::new_inner(uart, rx.map_into(), tx.map_into(), None, None, None, None, config)
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Self::new_inner(uart, tx.map_into(), rx.map_into(), None, None, None, None, config)
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}
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/// Create a new UART with hardware flow control (RTS/CTS)
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@ -211,8 +216,8 @@ impl<'d, T: Instance> Uart<'d, T, Blocking> {
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into_ref!(tx, rx, cts, rts);
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Self::new_inner(
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uart,
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rx.map_into(),
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tx.map_into(),
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rx.map_into(),
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Some(rts.map_into()),
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Some(cts.map_into()),
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None,
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@ -235,8 +240,8 @@ impl<'d, T: Instance> Uart<'d, T, Async> {
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into_ref!(tx, rx, tx_dma, rx_dma);
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Self::new_inner(
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uart,
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rx.map_into(),
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tx.map_into(),
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rx.map_into(),
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None,
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None,
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Some(tx_dma.map_into()),
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@ -259,8 +264,8 @@ impl<'d, T: Instance> Uart<'d, T, Async> {
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into_ref!(tx, rx, cts, rts, tx_dma, rx_dma);
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Self::new_inner(
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uart,
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rx.map_into(),
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tx.map_into(),
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rx.map_into(),
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Some(rts.map_into()),
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Some(cts.map_into()),
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Some(tx_dma.map_into()),
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@ -273,41 +278,52 @@ impl<'d, T: Instance> Uart<'d, T, Async> {
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impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
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fn new_inner(
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_uart: impl Peripheral<P = T> + 'd,
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tx: PeripheralRef<'d, AnyPin>,
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rx: PeripheralRef<'d, AnyPin>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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mut tx: PeripheralRef<'d, AnyPin>,
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mut rx: PeripheralRef<'d, AnyPin>,
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mut rts: Option<PeripheralRef<'d, AnyPin>>,
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mut cts: Option<PeripheralRef<'d, AnyPin>>,
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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config: Config,
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) -> Self {
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into_ref!(_uart);
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Self::init(
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Some(tx.reborrow()),
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Some(rx.reborrow()),
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rts.as_mut().map(|x| x.reborrow()),
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cts.as_mut().map(|x| x.reborrow()),
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config,
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);
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Self {
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tx: UartTx::new(tx_dma),
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rx: UartRx::new(rx_dma),
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}
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}
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fn init(
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tx: Option<PeripheralRef<'_, AnyPin>>,
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rx: Option<PeripheralRef<'_, AnyPin>>,
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rts: Option<PeripheralRef<'_, AnyPin>>,
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cts: Option<PeripheralRef<'_, AnyPin>>,
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config: Config,
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) {
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let r = T::regs();
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unsafe {
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let r = T::regs();
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tx.io().ctrl().write(|w| w.set_funcsel(2));
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rx.io().ctrl().write(|w| w.set_funcsel(2));
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tx.pad_ctrl().write(|w| {
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w.set_ie(true);
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});
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rx.pad_ctrl().write(|w| {
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w.set_ie(true);
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});
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if let Some(pin) = &tx {
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pin.io().ctrl().write(|w| w.set_funcsel(2));
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pin.pad_ctrl().write(|w| w.set_ie(true));
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}
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if let Some(pin) = &rx {
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pin.io().ctrl().write(|w| w.set_funcsel(2));
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pin.pad_ctrl().write(|w| w.set_ie(true));
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}
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if let Some(pin) = &cts {
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pin.io().ctrl().write(|w| w.set_funcsel(2));
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pin.pad_ctrl().write(|w| {
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w.set_ie(true);
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});
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pin.pad_ctrl().write(|w| w.set_ie(true));
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}
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if let Some(pin) = &rts {
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pin.io().ctrl().write(|w| w.set_funcsel(2));
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pin.pad_ctrl().write(|w| {
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w.set_ie(true);
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});
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pin.pad_ctrl().write(|w| w.set_ie(true));
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}
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let clk_base = crate::clocks::clk_peri_freq();
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@ -359,11 +375,6 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
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w.set_rtsen(rts.is_some());
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});
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}
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Self {
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tx: UartTx::new(tx_dma),
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rx: UartRx::new(rx_dma),
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}
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}
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}
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@ -611,11 +622,6 @@ mod eha {
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}
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}
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#[cfg(feature = "nightly")]
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mod buffered;
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#[cfg(feature = "nightly")]
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pub use buffered::*;
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mod sealed {
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use super::*;
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@ -628,6 +634,9 @@ mod sealed {
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type Interrupt: crate::interrupt::Interrupt;
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fn regs() -> pac::uart::Uart;
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#[cfg(feature = "nightly")]
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fn state() -> &'static buffered::State;
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}
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pub trait TxPin<T: Instance> {}
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pub trait RxPin<T: Instance> {}
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@ -663,6 +672,12 @@ macro_rules! impl_instance {
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fn regs() -> pac::uart::Uart {
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pac::$inst
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}
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#[cfg(feature = "nightly")]
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fn state() -> &'static buffered::State {
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static STATE: buffered::State = buffered::State::new();
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&STATE
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}
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}
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impl Instance for peripherals::$inst {}
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};
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