nrf: pwm clarify stop and disable pin state
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2bcacd4f16
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@ -308,19 +308,23 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
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Task::from_reg(&r.tasks_stop)
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}
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/// Stop playback.
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/// Stop playback. Does NOT clear the last duty cycle from the pin.
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#[inline(always)]
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pub fn stop(&self) {
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let r = T::regs();
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r.enable.write(|w| w.enable().disabled());
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r.shorts.reset();
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compiler_fence(Ordering::SeqCst);
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r.events_stopped.reset();
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// tasks_stop() doesn't exist in all svds so write its bit instead
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r.tasks_stop.write(|w| unsafe { w.bits(0x01) });
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while r.events_stopped.read().bits() == 0 {}
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r.enable.write(|w| w.enable().disabled());
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}
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}
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@ -513,19 +517,6 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
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pwm
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}
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/// Stop playback
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#[inline(always)]
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pub fn stop(&self) {
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let r = T::regs();
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r.shorts.reset();
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compiler_fence(Ordering::SeqCst);
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// tasks_stop() doesn't exist in all svds so write its bit instead
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r.tasks_stop.write(|w| unsafe { w.bits(0x01) });
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}
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/// Enables the PWM generator.
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#[inline(always)]
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pub fn enable(&self) {
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@ -533,7 +524,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
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r.enable.write(|w| w.enable().enabled());
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}
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/// Disables the PWM generator.
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/// Disables the PWM generator. Does NOT clear the last duty cycle from the pin.
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#[inline(always)]
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pub fn disable(&self) {
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let r = T::regs();
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@ -554,13 +545,14 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
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// defensive before seqstart
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compiler_fence(Ordering::SeqCst);
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r.events_seqend[0].reset();
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// tasks_seqstart() doesn't exist in all svds so write its bit instead
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r.tasks_seqstart[0].write(|w| unsafe { w.bits(1) });
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// defensive wait until waveform is loaded after seqstart so set_duty
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// can't be called again while dma is still reading
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while r.events_seqend[0].read().bits() == 0 {}
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r.events_seqend[0].write(|w| w);
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}
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/// Sets the PWM clock prescaler.
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@ -620,7 +612,6 @@ impl<'a, T: Instance> Drop for SimplePwm<'a, T> {
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fn drop(&mut self) {
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let r = T::regs();
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self.stop();
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self.disable();
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if let Some(pin) = &self.ch0 {
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