Rebase on master

embassy-rp/Cargo.toml

@@ -12,7 +12,7 @@ flavors = [
 ]
 
 [features]
-defmt = ["dep:defmt", "embassy-usb?/defmt"]
+defmt = ["dep:defmt", "embassy-usb-driver?/defmt"]
 
 # Reexport the PAC for the currently enabled chip at `embassy_rp::pac`.
 # This is unstable because semver-minor (non-breaking) releases of embassy-rp may major-bump (breaking) the PAC version.
@@ -23,11 +23,11 @@ unstable-pac = []
 time-driver = []
 
 rom-func-cache = []
-disable-intrinsics = []
+intrinsics = []
 rom-v2-intrinsics = []
 
 # Enable nightly-only features
-nightly = ["embassy-executor/nightly", "embedded-hal-1", "embedded-hal-async", "embassy-embedded-hal/nightly", "dep:embassy-usb"]
+nightly = ["embassy-executor/nightly", "embedded-hal-1", "embedded-hal-async", "embassy-embedded-hal/nightly", "dep:embassy-usb-driver", "dep:embedded-io"]
 
 # Implement embedded-hal 1.0 alpha traits.
 # Implement embedded-hal-async traits if `nightly` is set as well.
@@ -41,7 +41,7 @@ embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
 embassy-cortex-m = { version = "0.1.0", path = "../embassy-cortex-m", features = ["prio-bits-2"]}
 embassy-hal-common = {version = "0.1.0", path = "../embassy-hal-common" }
 embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" }
-embassy-usb = {version = "0.1.0", path = "../embassy-usb", optional = true }
+embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optional = true }
 atomic-polyfill = "1.0.1"
 defmt = { version = "0.3", optional = true }
 log = { version = "0.4.14", optional = true }
@@ -53,6 +53,7 @@ critical-section = "1.1"
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
 chrono = { version = "0.4", default-features = false, optional = true }
 embedded-storage = { version = "0.3" }
+embedded-io = { version = "0.3.0", features = ["async"], optional = true }
 
 rp2040-pac2 = { git = "https://github.com/embassy-rs/rp2040-pac2", rev="017e3c9007b2d3b6965f0d85b5bf8ce3fa6d7364", features = ["rt"] }
 #rp2040-pac2 = { path = "../../rp2040-pac2", features = ["rt"] }

embassy-rp/src/i2c.rs

@@ -0,0 +1,556 @@
+use core::marker::PhantomData;
+
+use embassy_hal_common::{into_ref, PeripheralRef};
+use pac::i2c;
+
+use crate::dma::AnyChannel;
+use crate::gpio::sealed::Pin;
+use crate::gpio::AnyPin;
+use crate::{pac, peripherals, Peripheral};
+
+/// I2C error abort reason
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum AbortReason {
+    /// A bus operation was not acknowledged, e.g. due to the addressed device
+    /// not being available on the bus or the device not being ready to process
+    /// requests at the moment
+    NoAcknowledge,
+    /// The arbitration was lost, e.g. electrical problems with the clock signal
+    ArbitrationLoss,
+    Other(u32),
+}
+
+/// I2C error
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// I2C abort with error
+    Abort(AbortReason),
+    /// User passed in a read buffer that was 0 length
+    InvalidReadBufferLength,
+    /// User passed in a write buffer that was 0 length
+    InvalidWriteBufferLength,
+    /// Target i2c address is out of range
+    AddressOutOfRange(u16),
+    /// Target i2c address is reserved
+    AddressReserved(u16),
+}
+
+#[non_exhaustive]
+#[derive(Copy, Clone)]
+pub struct Config {
+    pub frequency: u32,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self { frequency: 100_000 }
+    }
+}
+
+const FIFO_SIZE: u8 = 16;
+
+pub struct I2c<'d, T: Instance, M: Mode> {
+    _tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
+    _rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
+    _dma_buf: [u16; 256],
+    phantom: PhantomData<(&'d mut T, M)>,
+}
+
+impl<'d, T: Instance> I2c<'d, T, Blocking> {
+    pub fn new_blocking(
+        _peri: impl Peripheral<P = T> + 'd,
+        scl: impl Peripheral<P = impl SclPin<T>> + 'd,
+        sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
+        config: Config,
+    ) -> Self {
+        into_ref!(scl, sda);
+        Self::new_inner(_peri, scl.map_into(), sda.map_into(), None, None, config)
+    }
+}
+
+impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
+    fn new_inner(
+        _peri: impl Peripheral<P = T> + 'd,
+        scl: PeripheralRef<'d, AnyPin>,
+        sda: PeripheralRef<'d, AnyPin>,
+        _tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
+        _rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
+        config: Config,
+    ) -> Self {
+        into_ref!(_peri);
+
+        assert!(config.frequency <= 1_000_000);
+        assert!(config.frequency > 0);
+
+        let p = T::regs();
+
+        unsafe {
+            p.ic_enable().write(|w| w.set_enable(false));
+
+            // Select controller mode & speed
+            p.ic_con().modify(|w| {
+                // Always use "fast" mode (<= 400 kHz, works fine for standard
+                // mode too)
+                w.set_speed(i2c::vals::Speed::FAST);
+                w.set_master_mode(true);
+                w.set_ic_slave_disable(true);
+                w.set_ic_restart_en(true);
+                w.set_tx_empty_ctrl(true);
+            });
+
+            // Set FIFO watermarks to 1 to make things simpler. This is encoded
+            // by a register value of 0.
+            p.ic_tx_tl().write(|w| w.set_tx_tl(0));
+            p.ic_rx_tl().write(|w| w.set_rx_tl(0));
+
+            // Configure SCL & SDA pins
+            scl.io().ctrl().write(|w| w.set_funcsel(3));
+            sda.io().ctrl().write(|w| w.set_funcsel(3));
+
+            scl.pad_ctrl().write(|w| {
+                w.set_schmitt(true);
+                w.set_ie(true);
+                w.set_od(false);
+                w.set_pue(true);
+                w.set_pde(false);
+            });
+            sda.pad_ctrl().write(|w| {
+                w.set_schmitt(true);
+                w.set_ie(true);
+                w.set_od(false);
+                w.set_pue(true);
+                w.set_pde(false);
+            });
+
+            // Configure baudrate
+
+            // There are some subtleties to I2C timing which we are completely
+            // ignoring here See:
+            // https://github.com/raspberrypi/pico-sdk/blob/bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7/src/rp2_common/hardware_i2c/i2c.c#L69
+            let clk_base = crate::clocks::clk_peri_freq();
+
+            let period = (clk_base + config.frequency / 2) / config.frequency;
+            let lcnt = period * 3 / 5; // spend 3/5 (60%) of the period low
+            let hcnt = period - lcnt; // and 2/5 (40%) of the period high
+
+            // Check for out-of-range divisors:
+            assert!(hcnt <= 0xffff);
+            assert!(lcnt <= 0xffff);
+            assert!(hcnt >= 8);
+            assert!(lcnt >= 8);
+
+            // Per I2C-bus specification a device in standard or fast mode must
+            // internally provide a hold time of at least 300ns for the SDA
+            // signal to bridge the undefined region of the falling edge of SCL.
+            // A smaller hold time of 120ns is used for fast mode plus.
+            let sda_tx_hold_count = if config.frequency < 1_000_000 {
+                // sda_tx_hold_count = clk_base [cycles/s] * 300ns * (1s /
+                // 1e9ns) Reduce 300/1e9 to 3/1e7 to avoid numbers that don't
+                // fit in uint. Add 1 to avoid division truncation.
+                ((clk_base * 3) / 10_000_000) + 1
+            } else {
+                // fast mode plus requires a clk_base > 32MHz
+                assert!(clk_base >= 32_000_000);
+
+                // sda_tx_hold_count = clk_base [cycles/s] * 120ns * (1s /
+                // 1e9ns) Reduce 120/1e9 to 3/25e6 to avoid numbers that don't
+                // fit in uint. Add 1 to avoid division truncation.
+                ((clk_base * 3) / 25_000_000) + 1
+            };
+            assert!(sda_tx_hold_count <= lcnt - 2);
+
+            p.ic_fs_scl_hcnt().write(|w| w.set_ic_fs_scl_hcnt(hcnt as u16));
+            p.ic_fs_scl_lcnt().write(|w| w.set_ic_fs_scl_lcnt(lcnt as u16));
+            p.ic_fs_spklen()
+                .write(|w| w.set_ic_fs_spklen(if lcnt < 16 { 1 } else { (lcnt / 16) as u8 }));
+            p.ic_sda_hold()
+                .modify(|w| w.set_ic_sda_tx_hold(sda_tx_hold_count as u16));
+
+            // Enable I2C block
+            p.ic_enable().write(|w| w.set_enable(true));
+        }
+
+        Self {
+            _tx_dma,
+            _rx_dma,
+            _dma_buf: [0; 256],
+            phantom: PhantomData,
+        }
+    }
+
+    fn setup(addr: u16) -> Result<(), Error> {
+        if addr >= 0x80 {
+            return Err(Error::AddressOutOfRange(addr));
+        }
+
+        if i2c_reserved_addr(addr) {
+            return Err(Error::AddressReserved(addr));
+        }
+
+        let p = T::regs();
+        unsafe {
+            p.ic_enable().write(|w| w.set_enable(false));
+            p.ic_tar().write(|w| w.set_ic_tar(addr));
+            p.ic_enable().write(|w| w.set_enable(true));
+        }
+        Ok(())
+    }
+
+    fn read_and_clear_abort_reason(&mut self) -> Result<(), Error> {
+        let p = T::regs();
+        unsafe {
+            let abort_reason = p.ic_tx_abrt_source().read();
+            if abort_reason.0 != 0 {
+                // Note clearing the abort flag also clears the reason, and this
+                // instance of flag is clear-on-read! Note also the
+                // IC_CLR_TX_ABRT register always reads as 0.
+                p.ic_clr_tx_abrt().read();
+
+                let reason = if abort_reason.abrt_7b_addr_noack()
+                    | abort_reason.abrt_10addr1_noack()
+                    | abort_reason.abrt_10addr2_noack()
+                {
+                    AbortReason::NoAcknowledge
+                } else if abort_reason.arb_lost() {
+                    AbortReason::ArbitrationLoss
+                } else {
+                    AbortReason::Other(abort_reason.0)
+                };
+
+                Err(Error::Abort(reason))
+            } else {
+                Ok(())
+            }
+        }
+    }
+
+    fn read_blocking_internal(&mut self, buffer: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
+        if buffer.is_empty() {
+            return Err(Error::InvalidReadBufferLength);
+        }
+
+        let p = T::regs();
+        let lastindex = buffer.len() - 1;
+        for (i, byte) in buffer.iter_mut().enumerate() {
+            let first = i == 0;
+            let last = i == lastindex;
+
+            // NOTE(unsafe) We have &mut self
+            unsafe {
+                // wait until there is space in the FIFO to write the next byte
+                while p.ic_txflr().read().txflr() == FIFO_SIZE {}
+
+                p.ic_data_cmd().write(|w| {
+                    w.set_restart(restart && first);
+                    w.set_stop(send_stop && last);
+
+                    w.set_cmd(true);
+                });
+
+                while p.ic_rxflr().read().rxflr() == 0 {
+                    self.read_and_clear_abort_reason()?;
+                }
+
+                *byte = p.ic_data_cmd().read().dat();
+            }
+        }
+
+        Ok(())
+    }
+
+    fn write_blocking_internal(&mut self, bytes: &[u8], send_stop: bool) -> Result<(), Error> {
+        if bytes.is_empty() {
+            return Err(Error::InvalidWriteBufferLength);
+        }
+
+        let p = T::regs();
+
+        for (i, byte) in bytes.iter().enumerate() {
+            let last = i == bytes.len() - 1;
+
+            // NOTE(unsafe) We have &mut self
+            unsafe {
+                p.ic_data_cmd().write(|w| {
+                    w.set_stop(send_stop && last);
+                    w.set_dat(*byte);
+                });
+
+                // Wait until the transmission of the address/data from the
+                // internal shift register has completed. For this to function
+                // correctly, the TX_EMPTY_CTRL flag in IC_CON must be set. The
+                // TX_EMPTY_CTRL flag was set in i2c_init.
+                while !p.ic_raw_intr_stat().read().tx_empty() {}
+
+                let abort_reason = self.read_and_clear_abort_reason();
+
+                if abort_reason.is_err() || (send_stop && last) {
+                    // If the transaction was aborted or if it completed
+                    // successfully wait until the STOP condition has occured.
+
+                    while !p.ic_raw_intr_stat().read().stop_det() {}
+
+                    p.ic_clr_stop_det().read().clr_stop_det();
+                }
+
+                // Note the hardware issues a STOP automatically on an abort
+                // condition. Note also the hardware clears RX FIFO as well as
+                // TX on abort, ecause we set hwparam
+                // IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
+                abort_reason?;
+            }
+        }
+        Ok(())
+    }
+
+    // =========================
+    // Blocking public API
+    // =========================
+
+    pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
+        Self::setup(address.into())?;
+        self.read_blocking_internal(buffer, true, true)
+        // Automatic Stop
+    }
+
+    pub fn blocking_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
+        Self::setup(address.into())?;
+        self.write_blocking_internal(bytes, true)
+    }
+
+    pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
+        Self::setup(address.into())?;
+        self.write_blocking_internal(bytes, false)?;
+        self.read_blocking_internal(buffer, true, true)
+        // Automatic Stop
+    }
+}
+
+mod eh02 {
+    use super::*;
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> {
+        type Error = Error;
+
+        fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
+            self.blocking_read(address, buffer)
+        }
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> {
+        type Error = Error;
+
+        fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
+            self.blocking_write(address, bytes)
+        }
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> {
+        type Error = Error;
+
+        fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
+            self.blocking_write_read(address, bytes, buffer)
+        }
+    }
+}
+
+#[cfg(feature = "unstable-traits")]
+mod eh1 {
+    use super::*;
+
+    impl embedded_hal_1::i2c::Error for Error {
+        fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
+            match *self {
+                Self::Abort(AbortReason::ArbitrationLoss) => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
+                Self::Abort(AbortReason::NoAcknowledge) => {
+                    embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address)
+                }
+                Self::Abort(AbortReason::Other(_)) => embedded_hal_1::i2c::ErrorKind::Other,
+                Self::InvalidReadBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
+                Self::InvalidWriteBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
+                Self::AddressOutOfRange(_) => embedded_hal_1::i2c::ErrorKind::Other,
+                Self::AddressReserved(_) => embedded_hal_1::i2c::ErrorKind::Other,
+            }
+        }
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, T, M> {
+        type Error = Error;
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::blocking::I2c for I2c<'d, T, M> {
+        fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
+            self.blocking_read(address, buffer)
+        }
+
+        fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Self::Error> {
+            self.blocking_write(address, buffer)
+        }
+
+        fn write_iter<B>(&mut self, address: u8, bytes: B) -> Result<(), Self::Error>
+        where
+            B: IntoIterator<Item = u8>,
+        {
+            let mut peekable = bytes.into_iter().peekable();
+            Self::setup(address.into())?;
+
+            while let Some(tx) = peekable.next() {
+                self.write_blocking_internal(&[tx], peekable.peek().is_none())?;
+            }
+            Ok(())
+        }
+
+        fn write_iter_read<B>(&mut self, address: u8, bytes: B, buffer: &mut [u8]) -> Result<(), Self::Error>
+        where
+            B: IntoIterator<Item = u8>,
+        {
+            let peekable = bytes.into_iter().peekable();
+            Self::setup(address.into())?;
+
+            for tx in peekable {
+                self.write_blocking_internal(&[tx], false)?
+            }
+            self.read_blocking_internal(buffer, true, true)
+        }
+
+        fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
+            self.blocking_write_read(address, wr_buffer, rd_buffer)
+        }
+
+        fn transaction<'a>(
+            &mut self,
+            address: u8,
+            operations: &mut [embedded_hal_1::i2c::blocking::Operation<'a>],
+        ) -> Result<(), Self::Error> {
+            Self::setup(address.into())?;
+            for i in 0..operations.len() {
+                let last = i == operations.len() - 1;
+                match &mut operations[i] {
+                    embedded_hal_1::i2c::blocking::Operation::Read(buf) => {
+                        self.read_blocking_internal(buf, false, last)?
+                    }
+                    embedded_hal_1::i2c::blocking::Operation::Write(buf) => self.write_blocking_internal(buf, last)?,
+                }
+            }
+            Ok(())
+        }
+
+        fn transaction_iter<'a, O>(&mut self, address: u8, operations: O) -> Result<(), Self::Error>
+        where
+            O: IntoIterator<Item = embedded_hal_1::i2c::blocking::Operation<'a>>,
+        {
+            Self::setup(address.into())?;
+            let mut peekable = operations.into_iter().peekable();
+            while let Some(operation) = peekable.next() {
+                let last = peekable.peek().is_none();
+                match operation {
+                    embedded_hal_1::i2c::blocking::Operation::Read(buf) => {
+                        self.read_blocking_internal(buf, false, last)?
+                    }
+                    embedded_hal_1::i2c::blocking::Operation::Write(buf) => self.write_blocking_internal(buf, last)?,
+                }
+            }
+            Ok(())
+        }
+    }
+}
+
+fn i2c_reserved_addr(addr: u16) -> bool {
+    (addr & 0x78) == 0 || (addr & 0x78) == 0x78
+}
+
+mod sealed {
+    use embassy_cortex_m::interrupt::Interrupt;
+
+    pub trait Instance {
+        const TX_DREQ: u8;
+        const RX_DREQ: u8;
+
+        type Interrupt: Interrupt;
+
+        fn regs() -> crate::pac::i2c::I2c;
+    }
+
+    pub trait Mode {}
+
+    pub trait SdaPin<T: Instance> {}
+    pub trait SclPin<T: Instance> {}
+}
+
+pub trait Mode: sealed::Mode {}
+
+macro_rules! impl_mode {
+    ($name:ident) => {
+        impl sealed::Mode for $name {}
+        impl Mode for $name {}
+    };
+}
+
+pub struct Blocking;
+pub struct Async;
+
+impl_mode!(Blocking);
+impl_mode!(Async);
+
+pub trait Instance: sealed::Instance {}
+
+macro_rules! impl_instance {
+    ($type:ident, $irq:ident, $tx_dreq:expr, $rx_dreq:expr) => {
+        impl sealed::Instance for peripherals::$type {
+            const TX_DREQ: u8 = $tx_dreq;
+            const RX_DREQ: u8 = $rx_dreq;
+
+            type Interrupt = crate::interrupt::$irq;
+
+            fn regs() -> pac::i2c::I2c {
+                pac::$type
+            }
+        }
+        impl Instance for peripherals::$type {}
+    };
+}
+
+impl_instance!(I2C0, I2C0_IRQ, 32, 33);
+impl_instance!(I2C1, I2C1_IRQ, 34, 35);
+
+pub trait SdaPin<T: Instance>: sealed::SdaPin<T> + crate::gpio::Pin {}
+pub trait SclPin<T: Instance>: sealed::SclPin<T> + crate::gpio::Pin {}
+
+macro_rules! impl_pin {
+    ($pin:ident, $instance:ident, $function:ident) => {
+        impl sealed::$function<peripherals::$instance> for peripherals::$pin {}
+        impl $function<peripherals::$instance> for peripherals::$pin {}
+    };
+}
+
+impl_pin!(PIN_0, I2C0, SdaPin);
+impl_pin!(PIN_1, I2C0, SclPin);
+impl_pin!(PIN_2, I2C1, SdaPin);
+impl_pin!(PIN_3, I2C1, SclPin);
+impl_pin!(PIN_4, I2C0, SdaPin);
+impl_pin!(PIN_5, I2C0, SclPin);
+impl_pin!(PIN_6, I2C1, SdaPin);
+impl_pin!(PIN_7, I2C1, SclPin);
+impl_pin!(PIN_8, I2C0, SdaPin);
+impl_pin!(PIN_9, I2C0, SclPin);
+impl_pin!(PIN_10, I2C1, SdaPin);
+impl_pin!(PIN_11, I2C1, SclPin);
+impl_pin!(PIN_12, I2C0, SdaPin);
+impl_pin!(PIN_13, I2C0, SclPin);
+impl_pin!(PIN_14, I2C1, SdaPin);
+impl_pin!(PIN_15, I2C1, SclPin);
+impl_pin!(PIN_16, I2C0, SdaPin);
+impl_pin!(PIN_17, I2C0, SclPin);
+impl_pin!(PIN_18, I2C1, SdaPin);
+impl_pin!(PIN_19, I2C1, SclPin);
+impl_pin!(PIN_20, I2C0, SdaPin);
+impl_pin!(PIN_21, I2C0, SclPin);
+impl_pin!(PIN_22, I2C1, SdaPin);
+impl_pin!(PIN_23, I2C1, SclPin);
+impl_pin!(PIN_24, I2C0, SdaPin);
+impl_pin!(PIN_25, I2C0, SclPin);
+impl_pin!(PIN_26, I2C1, SdaPin);
+impl_pin!(PIN_27, I2C1, SclPin);
+impl_pin!(PIN_28, I2C0, SdaPin);
+impl_pin!(PIN_29, I2C0, SclPin);

embassy-rp/src/intrinsics.rs

@@ -1,4 +1,6 @@
 #![macro_use]
+// Credit: taken from `rp-hal` (also licensed Apache+MIT)
+// https://github.com/rp-rs/rp-hal/blob/main/rp2040-hal/src/intrinsics.rs
 
 /// Generate a series of aliases for an intrinsic function.
 macro_rules! intrinsics_aliases {
@@ -14,7 +16,7 @@ macro_rules! intrinsics_aliases {
         $alias:ident
         $($rest:ident)*
     ) => {
-        #[cfg(all(target_arch = "arm", not(feature = "disable-intrinsics")))]
+        #[cfg(all(target_arch = "arm", feature = "intrinsics"))]
         intrinsics! {
             extern $abi fn $alias( $($argname: $ty),* ) -> $ret {
                 $name($($argname),*)
@@ -32,7 +34,7 @@ macro_rules! intrinsics_aliases {
         $alias:ident
         $($rest:ident)*
     ) => {
-        #[cfg(all(target_arch = "arm", not(feature = "disable-intrinsics")))]
+        #[cfg(all(target_arch = "arm", feature = "intrinsics"))]
         intrinsics! {
             unsafe extern $abi fn $alias( $($argname: $ty),* ) -> $ret {
                 $name($($argname),*)
@@ -52,7 +54,7 @@ macro_rules! intrinsics_aliases {
 /// is to abstract anything special that needs to be done to override an
 /// intrinsic function.  Intrinsic generation is disabled for non-ARM targets
 /// so things like CI and docs generation do not have problems.  Additionally
-/// they can be disabled with the crate feature `disable-intrinsics` for
+/// they can be disabled by disabling the crate feature `intrinsics` for
 /// testing or comparing performance.
 ///
 /// Like the compiler-builtins macro, it accepts a series of functions that
@@ -211,13 +213,13 @@ macro_rules! intrinsics {
 
         $($rest:tt)*
     ) => {
-        #[cfg(all(target_arch = "arm", not(feature = "disable-intrinsics")))]
+        #[cfg(all(target_arch = "arm", feature = "intrinsics"))]
         $(#[$($attr)*])*
         extern $abi fn $name( $($argname: $ty),* ) -> $ret {
             $($body)*
         }
 
-        #[cfg(all(target_arch = "arm", not(feature = "disable-intrinsics")))]
+        #[cfg(all(target_arch = "arm", feature = "intrinsics"))]
         mod $name {
             #[no_mangle]
             $(#[$($attr)*])*
@@ -228,7 +230,7 @@ macro_rules! intrinsics {
 
         // Not exported, but defined so the actual implementation is
         // considered used
-        #[cfg(not(all(target_arch = "arm", not(feature = "disable-intrinsics"))))]
+        #[cfg(not(all(target_arch = "arm", feature = "intrinsics")))]
         #[allow(dead_code)]
         fn $name( $($argname: $ty),* ) -> $ret {
             $($body)*
@@ -245,13 +247,13 @@ macro_rules! intrinsics {
 
         $($rest:tt)*
     ) => {
-        #[cfg(all(target_arch = "arm", not(feature = "disable-intrinsics")))]
+        #[cfg(all(target_arch = "arm", feature = "intrinsics"))]
         $(#[$($attr)*])*
         unsafe extern $abi fn $name( $($argname: $ty),* ) -> $ret {
             $($body)*
         }
 
-        #[cfg(all(target_arch = "arm", not(feature = "disable-intrinsics")))]
+        #[cfg(all(target_arch = "arm", feature = "intrinsics"))]
         mod $name {
             #[no_mangle]
             $(#[$($attr)*])*
@@ -262,7 +264,7 @@ macro_rules! intrinsics {
 
         // Not exported, but defined so the actual implementation is
         // considered used
-        #[cfg(not(all(target_arch = "arm", not(feature = "disable-intrinsics"))))]
+        #[cfg(not(all(target_arch = "arm", feature = "intrinsics")))]
         #[allow(dead_code)]
         unsafe fn $name( $($argname: $ty),* ) -> $ret {
             $($body)*

embassy-rp/src/lib.rs

@@ -8,6 +8,7 @@ mod intrinsics;
 
 pub mod dma;
 pub mod gpio;
+pub mod i2c;
 pub mod interrupt;
 pub mod rom_data;
 pub mod rtc;
@@ -76,6 +77,9 @@ embassy_hal_common::peripherals! {
     SPI0,
     SPI1,
 
+    I2C0,
+    I2C1,
+
     DMA_CH0,
     DMA_CH1,
     DMA_CH2,

embassy-rp/src/rom_data.rs

@@ -7,6 +7,8 @@
 //! > on the device, as well as highly optimized versions of certain key
 //! > functionality that would otherwise have to take up space in most user
 //! > binaries.
+// Credit: taken from `rp-hal` (also licensed Apache+MIT)
+// https://github.com/rp-rs/rp-hal/blob/main/rp2040-hal/src/rom_data.rs
 
 /// A bootrom function table code.
 pub type RomFnTableCode = [u8; 2];

embassy-rp/src/uart/buffered.rs

@@ -0,0 +1,489 @@
+use core::future::{poll_fn, Future};
+use core::task::{Poll, Waker};
+
+use atomic_polyfill::{compiler_fence, Ordering};
+use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
+use embassy_hal_common::ring_buffer::RingBuffer;
+use embassy_sync::waitqueue::WakerRegistration;
+
+use super::*;
+
+pub struct State<'d, T: Instance>(StateStorage<FullStateInner<'d, T>>);
+impl<'d, T: Instance> State<'d, T> {
+    pub const fn new() -> Self {
+        Self(StateStorage::new())
+    }
+}
+
+pub struct RxState<'d, T: Instance>(StateStorage<RxStateInner<'d, T>>);
+impl<'d, T: Instance> RxState<'d, T> {
+    pub const fn new() -> Self {
+        Self(StateStorage::new())
+    }
+}
+
+pub struct TxState<'d, T: Instance>(StateStorage<TxStateInner<'d, T>>);
+impl<'d, T: Instance> TxState<'d, T> {
+    pub const fn new() -> Self {
+        Self(StateStorage::new())
+    }
+}
+
+struct RxStateInner<'d, T: Instance> {
+    phantom: PhantomData<&'d mut T>,
+
+    waker: WakerRegistration,
+    buf: RingBuffer<'d>,
+}
+
+struct TxStateInner<'d, T: Instance> {
+    phantom: PhantomData<&'d mut T>,
+
+    waker: WakerRegistration,
+    buf: RingBuffer<'d>,
+}
+
+struct FullStateInner<'d, T: Instance> {
+    rx: RxStateInner<'d, T>,
+    tx: TxStateInner<'d, T>,
+}
+
+unsafe impl<'d, T: Instance> Send for RxStateInner<'d, T> {}
+unsafe impl<'d, T: Instance> Sync for RxStateInner<'d, T> {}
+
+unsafe impl<'d, T: Instance> Send for TxStateInner<'d, T> {}
+unsafe impl<'d, T: Instance> Sync for TxStateInner<'d, T> {}
+
+unsafe impl<'d, T: Instance> Send for FullStateInner<'d, T> {}
+unsafe impl<'d, T: Instance> Sync for FullStateInner<'d, T> {}
+
+pub struct BufferedUart<'d, T: Instance> {
+    inner: PeripheralMutex<'d, FullStateInner<'d, T>>,
+}
+
+pub struct BufferedUartRx<'d, T: Instance> {
+    inner: PeripheralMutex<'d, RxStateInner<'d, T>>,
+}
+
+pub struct BufferedUartTx<'d, T: Instance> {
+    inner: PeripheralMutex<'d, TxStateInner<'d, T>>,
+}
+
+impl<'d, T: Instance> Unpin for BufferedUart<'d, T> {}
+impl<'d, T: Instance> Unpin for BufferedUartRx<'d, T> {}
+impl<'d, T: Instance> Unpin for BufferedUartTx<'d, T> {}
+
+impl<'d, T: Instance> BufferedUart<'d, T> {
+    pub fn new<M: Mode>(
+        state: &'d mut State<'d, T>,
+        _uart: Uart<'d, T, M>,
+        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+    ) -> BufferedUart<'d, T> {
+        into_ref!(irq);
+
+        let r = T::regs();
+        unsafe {
+            r.uartimsc().modify(|w| {
+                w.set_rxim(true);
+                w.set_rtim(true);
+                w.set_txim(true);
+            });
+        }
+
+        Self {
+            inner: PeripheralMutex::new(irq, &mut state.0, move || FullStateInner {
+                tx: TxStateInner {
+                    phantom: PhantomData,
+                    waker: WakerRegistration::new(),
+                    buf: RingBuffer::new(tx_buffer),
+                },
+                rx: RxStateInner {
+                    phantom: PhantomData,
+                    waker: WakerRegistration::new(),
+                    buf: RingBuffer::new(rx_buffer),
+                },
+            }),
+        }
+    }
+}
+
+impl<'d, T: Instance> BufferedUartRx<'d, T> {
+    pub fn new<M: Mode>(
+        state: &'d mut RxState<'d, T>,
+        _uart: UartRx<'d, T, M>,
+        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        rx_buffer: &'d mut [u8],
+    ) -> BufferedUartRx<'d, T> {
+        into_ref!(irq);
+
+        let r = T::regs();
+        unsafe {
+            r.uartimsc().modify(|w| {
+                w.set_rxim(true);
+                w.set_rtim(true);
+            });
+        }
+
+        Self {
+            inner: PeripheralMutex::new(irq, &mut state.0, move || RxStateInner {
+                phantom: PhantomData,
+
+                buf: RingBuffer::new(rx_buffer),
+                waker: WakerRegistration::new(),
+            }),
+        }
+    }
+}
+
+impl<'d, T: Instance> BufferedUartTx<'d, T> {
+    pub fn new<M: Mode>(
+        state: &'d mut TxState<'d, T>,
+        _uart: UartTx<'d, T, M>,
+        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        tx_buffer: &'d mut [u8],
+    ) -> BufferedUartTx<'d, T> {
+        into_ref!(irq);
+
+        let r = T::regs();
+        unsafe {
+            r.uartimsc().modify(|w| {
+                w.set_txim(true);
+            });
+        }
+
+        Self {
+            inner: PeripheralMutex::new(irq, &mut state.0, move || TxStateInner {
+                phantom: PhantomData,
+
+                buf: RingBuffer::new(tx_buffer),
+                waker: WakerRegistration::new(),
+            }),
+        }
+    }
+}
+
+impl<'d, T: Instance> PeripheralState for FullStateInner<'d, T>
+where
+    Self: 'd,
+{
+    type Interrupt = T::Interrupt;
+    fn on_interrupt(&mut self) {
+        self.rx.on_interrupt();
+        self.tx.on_interrupt();
+    }
+}
+
+impl<'d, T: Instance> RxStateInner<'d, T>
+where
+    Self: 'd,
+{
+    fn read(&mut self, buf: &mut [u8], waker: &Waker) -> (Poll<Result<usize, Error>>, bool) {
+        // We have data ready in buffer? Return it.
+        let mut do_pend = false;
+        let data = self.buf.pop_buf();
+        if !data.is_empty() {
+            let len = data.len().min(buf.len());
+            buf[..len].copy_from_slice(&data[..len]);
+
+            if self.buf.is_full() {
+                do_pend = true;
+            }
+            self.buf.pop(len);
+
+            return (Poll::Ready(Ok(len)), do_pend);
+        }
+
+        self.waker.register(waker);
+        (Poll::Pending, do_pend)
+    }
+
+    fn fill_buf<'a>(&mut self, waker: &Waker) -> Poll<Result<&'a [u8], Error>> {
+        // We have data ready in buffer? Return it.
+        let buf = self.buf.pop_buf();
+        if !buf.is_empty() {
+            let buf: &[u8] = buf;
+            // Safety: buffer lives as long as uart
+            let buf: &[u8] = unsafe { core::mem::transmute(buf) };
+            return Poll::Ready(Ok(buf));
+        }
+
+        self.waker.register(waker);
+        Poll::Pending
+    }
+
+    fn consume(&mut self, amt: usize) -> bool {
+        let full = self.buf.is_full();
+        self.buf.pop(amt);
+        full
+    }
+}
+
+impl<'d, T: Instance> PeripheralState for RxStateInner<'d, T>
+where
+    Self: 'd,
+{
+    type Interrupt = T::Interrupt;
+    fn on_interrupt(&mut self) {
+        let r = T::regs();
+        unsafe {
+            let ris = r.uartris().read();
+            // Clear interrupt flags
+            r.uarticr().modify(|w| {
+                w.set_rxic(true);
+                w.set_rtic(true);
+            });
+
+            if ris.peris() {
+                warn!("Parity error");
+                r.uarticr().modify(|w| {
+                    w.set_peic(true);
+                });
+            }
+            if ris.feris() {
+                warn!("Framing error");
+                r.uarticr().modify(|w| {
+                    w.set_feic(true);
+                });
+            }
+            if ris.beris() {
+                warn!("Break error");
+                r.uarticr().modify(|w| {
+                    w.set_beic(true);
+                });
+            }
+            if ris.oeris() {
+                warn!("Overrun error");
+                r.uarticr().modify(|w| {
+                    w.set_oeic(true);
+                });
+            }
+
+            if !r.uartfr().read().rxfe() {
+                let buf = self.buf.push_buf();
+                if !buf.is_empty() {
+                    buf[0] = r.uartdr().read().data();
+                    self.buf.push(1);
+                } else {
+                    warn!("RX buffer full, discard received byte");
+                }
+
+                if self.buf.is_full() {
+                    self.waker.wake();
+                }
+            }
+
+            if ris.rtris() {
+                self.waker.wake();
+            };
+        }
+    }
+}
+
+impl<'d, T: Instance> TxStateInner<'d, T>
+where
+    Self: 'd,
+{
+    fn write(&mut self, buf: &[u8], waker: &Waker) -> (Poll<Result<usize, Error>>, bool) {
+        let empty = self.buf.is_empty();
+        let tx_buf = self.buf.push_buf();
+        if tx_buf.is_empty() {
+            self.waker.register(waker);
+            return (Poll::Pending, empty);
+        }
+
+        let n = core::cmp::min(tx_buf.len(), buf.len());
+        tx_buf[..n].copy_from_slice(&buf[..n]);
+        self.buf.push(n);
+
+        (Poll::Ready(Ok(n)), empty)
+    }
+
+    fn flush(&mut self, waker: &Waker) -> Poll<Result<(), Error>> {
+        if !self.buf.is_empty() {
+            self.waker.register(waker);
+            return Poll::Pending;
+        }
+
+        Poll::Ready(Ok(()))
+    }
+}
+
+impl<'d, T: Instance> PeripheralState for TxStateInner<'d, T>
+where
+    Self: 'd,
+{
+    type Interrupt = T::Interrupt;
+    fn on_interrupt(&mut self) {
+        let r = T::regs();
+        unsafe {
+            let buf = self.buf.pop_buf();
+            if !buf.is_empty() {
+                r.uartimsc().modify(|w| {
+                    w.set_txim(true);
+                });
+                r.uartdr().write(|w| w.set_data(buf[0].into()));
+                self.buf.pop(1);
+                self.waker.wake();
+            } else {
+                // Disable interrupt until we have something to transmit again
+                r.uartimsc().modify(|w| {
+                    w.set_txim(false);
+                });
+            }
+        }
+    }
+}
+
+impl embedded_io::Error for Error {
+    fn kind(&self) -> embedded_io::ErrorKind {
+        embedded_io::ErrorKind::Other
+    }
+}
+
+impl<'d, T: Instance> embedded_io::Io for BufferedUart<'d, T> {
+    type Error = Error;
+}
+
+impl<'d, T: Instance> embedded_io::Io for BufferedUartRx<'d, T> {
+    type Error = Error;
+}
+
+impl<'d, T: Instance> embedded_io::Io for BufferedUartTx<'d, T> {
+    type Error = Error;
+}
+
+impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> {
+    type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
+    where
+        Self: 'a;
+
+    fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
+        poll_fn(move |cx| {
+            let (res, do_pend) = self.inner.with(|state| {
+                compiler_fence(Ordering::SeqCst);
+                state.rx.read(buf, cx.waker())
+            });
+
+            if do_pend {
+                self.inner.pend();
+            }
+
+            res
+        })
+    }
+}
+
+impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUartRx<'d, T> {
+    type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
+    where
+        Self: 'a;
+
+    fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
+        poll_fn(move |cx| {
+            let (res, do_pend) = self.inner.with(|state| {
+                compiler_fence(Ordering::SeqCst);
+                state.read(buf, cx.waker())
+            });
+
+            if do_pend {
+                self.inner.pend();
+            }
+
+            res
+        })
+    }
+}
+
+impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T> {
+    type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>>
+    where
+        Self: 'a;
+
+    fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
+        poll_fn(move |cx| {
+            self.inner.with(|state| {
+                compiler_fence(Ordering::SeqCst);
+                state.rx.fill_buf(cx.waker())
+            })
+        })
+    }
+
+    fn consume(&mut self, amt: usize) {
+        let signal = self.inner.with(|state| state.rx.consume(amt));
+        if signal {
+            self.inner.pend();
+        }
+    }
+}
+
+impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUartRx<'d, T> {
+    type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>>
+    where
+        Self: 'a;
+
+    fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
+        poll_fn(move |cx| {
+            self.inner.with(|state| {
+                compiler_fence(Ordering::SeqCst);
+                state.fill_buf(cx.waker())
+            })
+        })
+    }
+
+    fn consume(&mut self, amt: usize) {
+        let signal = self.inner.with(|state| state.consume(amt));
+        if signal {
+            self.inner.pend();
+        }
+    }
+}
+
+impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> {
+    type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
+    where
+        Self: 'a;
+
+    fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
+        poll_fn(move |cx| {
+            let (poll, empty) = self.inner.with(|state| state.tx.write(buf, cx.waker()));
+            if empty {
+                self.inner.pend();
+            }
+            poll
+        })
+    }
+
+    type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>>
+    where
+        Self: 'a;
+
+    fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
+        poll_fn(move |cx| self.inner.with(|state| state.tx.flush(cx.waker())))
+    }
+}
+
+impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUartTx<'d, T> {
+    type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
+    where
+        Self: 'a;
+
+    fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
+        poll_fn(move |cx| {
+            let (poll, empty) = self.inner.with(|state| state.write(buf, cx.waker()));
+            if empty {
+                self.inner.pend();
+            }
+            poll
+        })
+    }
+
+    type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>>
+    where
+        Self: 'a;
+
+    fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
+        poll_fn(move |cx| self.inner.with(|state| state.flush(cx.waker())))
+    }
+}

embassy-rp/src/uart/mod.rs

@@ -346,6 +346,11 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
                 w.set_fen(true);
             });
 
+            r.uartifls().write(|w| {
+                w.set_rxiflsel(0b000);
+                w.set_txiflsel(0b000);
+            });
+
             r.uartcr().write(|w| {
                 w.set_uarten(true);
                 w.set_rxe(true);
@@ -423,9 +428,11 @@ mod eh02 {
 
     impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for UartTx<'d, T, M> {
         type Error = Error;
+
         fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
             self.blocking_write(buffer)
         }
+
         fn bflush(&mut self) -> Result<(), Self::Error> {
             self.blocking_flush()
         }
@@ -433,6 +440,7 @@ mod eh02 {
 
     impl<'d, T: Instance, M: Mode> embedded_hal_02::serial::Read<u8> for Uart<'d, T, M> {
         type Error = Error;
+
         fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
             embedded_hal_02::serial::Read::read(&mut self.rx)
         }
@@ -440,9 +448,11 @@ mod eh02 {
 
     impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for Uart<'d, T, M> {
         type Error = Error;
+
         fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
             self.blocking_write(buffer)
         }
+
         fn bflush(&mut self) -> Result<(), Self::Error> {
             self.blocking_flush()
         }
@@ -475,6 +485,75 @@ mod eh1 {
     impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::ErrorType for UartRx<'d, T, M> {
         type Error = Error;
     }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::nb::Read for UartRx<'d, T, M> {
+        fn read(&mut self) -> nb::Result<u8, Self::Error> {
+            let r = T::regs();
+            unsafe {
+                let dr = r.uartdr().read();
+
+                if dr.oe() {
+                    Err(nb::Error::Other(Error::Overrun))
+                } else if dr.be() {
+                    Err(nb::Error::Other(Error::Break))
+                } else if dr.pe() {
+                    Err(nb::Error::Other(Error::Parity))
+                } else if dr.fe() {
+                    Err(nb::Error::Other(Error::Framing))
+                } else if dr.fe() {
+                    Ok(dr.data())
+                } else {
+                    Err(nb::Error::WouldBlock)
+                }
+            }
+        }
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::blocking::Write for UartTx<'d, T, M> {
+        fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
+            self.blocking_write(buffer)
+        }
+
+        fn flush(&mut self) -> Result<(), Self::Error> {
+            self.blocking_flush()
+        }
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::nb::Write for UartTx<'d, T, M> {
+        fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
+            self.blocking_write(&[char]).map_err(nb::Error::Other)
+        }
+
+        fn flush(&mut self) -> nb::Result<(), Self::Error> {
+            self.blocking_flush().map_err(nb::Error::Other)
+        }
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::nb::Read for Uart<'d, T, M> {
+        fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
+            embedded_hal_02::serial::Read::read(&mut self.rx)
+        }
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::blocking::Write for Uart<'d, T, M> {
+        fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
+            self.blocking_write(buffer)
+        }
+
+        fn flush(&mut self) -> Result<(), Self::Error> {
+            self.blocking_flush()
+        }
+    }
+
+    impl<'d, T: Instance, M: Mode> embedded_hal_1::serial::nb::Write for Uart<'d, T, M> {
+        fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
+            self.blocking_write(&[char]).map_err(nb::Error::Other)
+        }
+
+        fn flush(&mut self) -> nb::Result<(), Self::Error> {
+            self.blocking_flush().map_err(nb::Error::Other)
+        }
+    }
 }
 
 #[cfg(all(
@@ -532,6 +611,11 @@ mod eha {
     }
 }
 
+#[cfg(feature = "nightly")]
+mod buffered;
+#[cfg(feature = "nightly")]
+pub use buffered::*;
+
 mod sealed {
     use super::*;
 
@@ -541,6 +625,8 @@ mod sealed {
         const TX_DREQ: u8;
         const RX_DREQ: u8;
 
+        type Interrupt: crate::interrupt::Interrupt;
+
         fn regs() -> pac::uart::Uart;
     }
     pub trait TxPin<T: Instance> {}
@@ -572,6 +658,8 @@ macro_rules! impl_instance {
             const TX_DREQ: u8 = $tx_dreq;
             const RX_DREQ: u8 = $rx_dreq;
 
+            type Interrupt = crate::interrupt::$irq;
+
             fn regs() -> pac::uart::Uart {
                 pac::$inst
             }
@@ -580,8 +668,8 @@ macro_rules! impl_instance {
     };
 }
 
-impl_instance!(UART0, UART0, 20, 21);
-impl_instance!(UART1, UART1, 22, 23);
+impl_instance!(UART0, UART0_IRQ, 20, 21);
+impl_instance!(UART1, UART1_IRQ, 22, 23);
 
 pub trait TxPin<T: Instance>: sealed::TxPin<T> + crate::gpio::Pin {}
 pub trait RxPin<T: Instance>: sealed::RxPin<T> + crate::gpio::Pin {}

embassy-rp/src/usb.rs

@@ -7,8 +7,10 @@ use core::task::Poll;
 use atomic_polyfill::compiler_fence;
 use embassy_hal_common::into_ref;
 use embassy_sync::waitqueue::AtomicWaker;
-use embassy_usb::driver::{self, EndpointAllocError, EndpointError, Event, Unsupported};
-use embassy_usb::types::{EndpointAddress, EndpointInfo, EndpointType, UsbDirection};
+use embassy_usb_driver as driver;
+use embassy_usb_driver::{
+    Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
+};
 
 use crate::interrupt::{Interrupt, InterruptExt};
 use crate::{pac, peripherals, Peripheral, RegExt};
@@ -204,8 +206,8 @@ impl<'d, T: Instance> Driver<'d, T> {
         );
 
         let alloc = match D::dir() {
-            UsbDirection::Out => &mut self.ep_out,
-            UsbDirection::In => &mut self.ep_in,
+            Direction::Out => &mut self.ep_out,
+            Direction::In => &mut self.ep_in,
         };
 
         let index = alloc.iter_mut().enumerate().find(|(i, ep)| {
@@ -254,7 +256,7 @@ impl<'d, T: Instance> Driver<'d, T> {
         };
 
         match D::dir() {
-            UsbDirection::Out => unsafe {
+            Direction::Out => unsafe {
                 T::dpram().ep_out_control(index - 1).write(|w| {
                     w.set_enable(false);
                     w.set_buffer_address(addr);
@@ -262,7 +264,7 @@ impl<'d, T: Instance> Driver<'d, T> {
                     w.set_endpoint_type(ep_type_reg);
                 })
             },
-            UsbDirection::In => unsafe {
+            Direction::In => unsafe {
                 T::dpram().ep_in_control(index - 1).write(|w| {
                     w.set_enable(false);
                     w.set_buffer_address(addr);
@@ -429,14 +431,14 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
 
         let n = ep_addr.index();
         match ep_addr.direction() {
-            UsbDirection::In => unsafe {
+            Direction::In => unsafe {
                 T::dpram().ep_in_control(n - 1).modify(|w| w.set_enable(enabled));
                 T::dpram().ep_in_buffer_control(ep_addr.index()).write(|w| {
                     w.set_pid(0, true); // first packet is DATA0, but PID is flipped before
                 });
                 EP_IN_WAKERS[n].wake();
             },
-            UsbDirection::Out => unsafe {
+            Direction::Out => unsafe {
                 T::dpram().ep_out_control(n - 1).modify(|w| w.set_enable(enabled));
 
                 T::dpram().ep_out_buffer_control(ep_addr.index()).write(|w| {
@@ -474,14 +476,14 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
 }
 
 trait Dir {
-    fn dir() -> UsbDirection;
+    fn dir() -> Direction;
     fn waker(i: usize) -> &'static AtomicWaker;
 }
 
 pub enum In {}
 impl Dir for In {
-    fn dir() -> UsbDirection {
-        UsbDirection::In
+    fn dir() -> Direction {
+        Direction::In
     }
 
     #[inline]
@@ -492,8 +494,8 @@ impl Dir for In {
 
 pub enum Out {}
 impl Dir for Out {
-    fn dir() -> UsbDirection {
-        UsbDirection::Out
+    fn dir() -> Direction {
+        Direction::Out
     }
 
     #[inline]