From 7ef58061680f3b37de5ba059926f1cb710512ad7 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sat, 1 May 2021 03:07:17 +0200 Subject: [PATCH] stm32: codegen interrupts --- embassy-extras/src/macros.rs | 12 +- embassy-macros/src/lib.rs | 73 +- embassy-stm32-examples/Cargo.toml | 2 +- embassy-stm32-examples/src/bin/blinky.rs | 3 +- embassy-stm32-examples/src/bin/button.rs | 3 +- embassy-stm32-examples/src/bin/button_exti.rs | 51 +- embassy-stm32-examples/src/bin/usart.rs | 8 +- embassy-stm32/Cargo.toml | 5 +- embassy-stm32/build.rs | 34 + embassy-stm32/gen.py | 68 +- embassy-stm32/src/chip/stm32f401cb.rs | 329 +++++ embassy-stm32/src/chip/stm32f401cc.rs | 329 +++++ embassy-stm32/src/chip/stm32f401cd.rs | 329 +++++ embassy-stm32/src/chip/stm32f401ce.rs | 329 +++++ embassy-stm32/src/chip/stm32f401rb.rs | 329 +++++ embassy-stm32/src/chip/stm32f401rc.rs | 329 +++++ embassy-stm32/src/chip/stm32f401rd.rs | 329 +++++ embassy-stm32/src/chip/stm32f401re.rs | 329 +++++ embassy-stm32/src/chip/stm32f401vb.rs | 329 +++++ embassy-stm32/src/chip/stm32f401vc.rs | 329 +++++ embassy-stm32/src/chip/stm32f401vd.rs | 329 +++++ embassy-stm32/src/chip/stm32f401ve.rs | 329 +++++ embassy-stm32/src/chip/stm32f405oe.rs | 404 +++++++ embassy-stm32/src/chip/stm32f405og.rs | 404 +++++++ embassy-stm32/src/chip/stm32f405rg.rs | 404 +++++++ embassy-stm32/src/chip/stm32f405vg.rs | 404 +++++++ embassy-stm32/src/chip/stm32f405zg.rs | 404 +++++++ embassy-stm32/src/chip/stm32f407ie.rs | 413 +++++++ embassy-stm32/src/chip/stm32f407ig.rs | 413 +++++++ embassy-stm32/src/chip/stm32f407ve.rs | 413 +++++++ embassy-stm32/src/chip/stm32f407vg.rs | 413 +++++++ embassy-stm32/src/chip/stm32f407ze.rs | 413 +++++++ embassy-stm32/src/chip/stm32f407zg.rs | 413 +++++++ embassy-stm32/src/chip/stm32f410c8.rs | 330 +++++ embassy-stm32/src/chip/stm32f410cb.rs | 330 +++++ embassy-stm32/src/chip/stm32f410r8.rs | 330 +++++ embassy-stm32/src/chip/stm32f410rb.rs | 330 +++++ embassy-stm32/src/chip/stm32f410t8.rs | 321 +++++ embassy-stm32/src/chip/stm32f410tb.rs | 321 +++++ embassy-stm32/src/chip/stm32f411cc.rs | 333 +++++ embassy-stm32/src/chip/stm32f411ce.rs | 333 +++++ embassy-stm32/src/chip/stm32f411rc.rs | 333 +++++ embassy-stm32/src/chip/stm32f411re.rs | 333 +++++ embassy-stm32/src/chip/stm32f411vc.rs | 333 +++++ embassy-stm32/src/chip/stm32f411ve.rs | 333 +++++ embassy-stm32/src/chip/stm32f412ce.rs | 418 +++++++ embassy-stm32/src/chip/stm32f412cg.rs | 418 +++++++ embassy-stm32/src/chip/stm32f412re.rs | 421 +++++++ embassy-stm32/src/chip/stm32f412rg.rs | 421 +++++++ embassy-stm32/src/chip/stm32f412ve.rs | 421 +++++++ embassy-stm32/src/chip/stm32f412vg.rs | 421 +++++++ embassy-stm32/src/chip/stm32f412ze.rs | 421 +++++++ embassy-stm32/src/chip/stm32f412zg.rs | 421 +++++++ embassy-stm32/src/chip/stm32f413cg.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413ch.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413mg.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413mh.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413rg.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413rh.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413vg.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413vh.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413zg.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f413zh.rs | 482 ++++++++ embassy-stm32/src/chip/stm32f415og.rs | 407 +++++++ embassy-stm32/src/chip/stm32f415rg.rs | 407 +++++++ embassy-stm32/src/chip/stm32f415vg.rs | 407 +++++++ embassy-stm32/src/chip/stm32f415zg.rs | 407 +++++++ embassy-stm32/src/chip/stm32f417ie.rs | 416 +++++++ embassy-stm32/src/chip/stm32f417ig.rs | 416 +++++++ embassy-stm32/src/chip/stm32f417ve.rs | 416 +++++++ embassy-stm32/src/chip/stm32f417vg.rs | 416 +++++++ embassy-stm32/src/chip/stm32f417ze.rs | 416 +++++++ embassy-stm32/src/chip/stm32f417zg.rs | 416 +++++++ embassy-stm32/src/chip/stm32f423ch.rs | 485 ++++++++ embassy-stm32/src/chip/stm32f423mh.rs | 485 ++++++++ embassy-stm32/src/chip/stm32f423rh.rs | 485 ++++++++ embassy-stm32/src/chip/stm32f423vh.rs | 485 ++++++++ embassy-stm32/src/chip/stm32f423zh.rs | 485 ++++++++ embassy-stm32/src/chip/stm32f427ag.rs | 443 +++++++ embassy-stm32/src/chip/stm32f427ai.rs | 443 +++++++ embassy-stm32/src/chip/stm32f427ig.rs | 443 +++++++ embassy-stm32/src/chip/stm32f427ii.rs | 443 +++++++ embassy-stm32/src/chip/stm32f427vg.rs | 443 +++++++ embassy-stm32/src/chip/stm32f427vi.rs | 443 +++++++ embassy-stm32/src/chip/stm32f427zg.rs | 443 +++++++ embassy-stm32/src/chip/stm32f427zi.rs | 443 +++++++ embassy-stm32/src/chip/stm32f429ag.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ai.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429be.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429bg.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429bi.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ie.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ig.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ii.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ne.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ng.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ni.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ve.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429vg.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429vi.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429ze.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429zg.rs | 449 +++++++ embassy-stm32/src/chip/stm32f429zi.rs | 449 +++++++ embassy-stm32/src/chip/stm32f437ai.rs | 446 +++++++ embassy-stm32/src/chip/stm32f437ig.rs | 446 +++++++ embassy-stm32/src/chip/stm32f437ii.rs | 446 +++++++ embassy-stm32/src/chip/stm32f437vg.rs | 446 +++++++ embassy-stm32/src/chip/stm32f437vi.rs | 446 +++++++ embassy-stm32/src/chip/stm32f437zg.rs | 446 +++++++ embassy-stm32/src/chip/stm32f437zi.rs | 446 +++++++ embassy-stm32/src/chip/stm32f439ai.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439bg.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439bi.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439ig.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439ii.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439ng.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439ni.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439vg.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439vi.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439zg.rs | 452 +++++++ embassy-stm32/src/chip/stm32f439zi.rs | 452 +++++++ embassy-stm32/src/chip/stm32f446mc.rs | 447 +++++++ embassy-stm32/src/chip/stm32f446me.rs | 447 +++++++ embassy-stm32/src/chip/stm32f446rc.rs | 447 +++++++ embassy-stm32/src/chip/stm32f446re.rs | 447 +++++++ embassy-stm32/src/chip/stm32f446vc.rs | 447 +++++++ embassy-stm32/src/chip/stm32f446ve.rs | 447 +++++++ embassy-stm32/src/chip/stm32f446zc.rs | 447 +++++++ embassy-stm32/src/chip/stm32f446ze.rs | 447 +++++++ embassy-stm32/src/chip/stm32f469ae.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ag.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ai.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469be.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469bg.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469bi.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ie.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ig.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ii.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ne.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ng.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ni.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ve.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469vg.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469vi.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469ze.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469zg.rs | 457 +++++++ embassy-stm32/src/chip/stm32f469zi.rs | 457 +++++++ embassy-stm32/src/chip/stm32f479ag.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479ai.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479bg.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479bi.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479ig.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479ii.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479ng.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479ni.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479vg.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479vi.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479zg.rs | 460 +++++++ embassy-stm32/src/chip/stm32f479zi.rs | 460 +++++++ embassy-stm32/src/exti.rs | 38 +- embassy-stm32/src/interrupt.rs | 1068 ----------------- embassy-stm32/src/lib.rs | 33 +- 162 files changed, 63977 insertions(+), 1151 deletions(-) create mode 100644 embassy-stm32/build.rs diff --git a/embassy-extras/src/macros.rs b/embassy-extras/src/macros.rs index d8543935..170ec078 100644 --- a/embassy-extras/src/macros.rs +++ b/embassy-extras/src/macros.rs @@ -46,17 +46,17 @@ macro_rules! peripherals { impl Peripherals { ///Returns all the peripherals *once* #[inline] - pub fn take() -> Option { + pub(crate) fn take() -> Self { #[no_mangle] static mut _EMBASSY_DEVICE_PERIPHERALS: bool = false; - cortex_m::interrupt::free(|_| { - if unsafe { _EMBASSY_DEVICE_PERIPHERALS } { - None + cortex_m::interrupt::free(|_| unsafe { + if _EMBASSY_DEVICE_PERIPHERALS { + panic!("init called twice") } else { - unsafe { _EMBASSY_DEVICE_PERIPHERALS = true }; - Some(unsafe { ::steal() }) + _EMBASSY_DEVICE_PERIPHERALS = true; + ::steal() } }) } diff --git a/embassy-macros/src/lib.rs b/embassy-macros/src/lib.rs index 45592a6e..16a47b9d 100644 --- a/embassy-macros/src/lib.rs +++ b/embassy-macros/src/lib.rs @@ -3,9 +3,13 @@ extern crate proc_macro; use darling::FromMeta; -use proc_macro::{Span, TokenStream}; +use proc_macro::TokenStream; +use proc_macro2::Span; use quote::{format_ident, quote}; +use std::iter; use syn::spanned::Spanned; +use syn::{parse, Type, Visibility}; +use syn::{ItemFn, ReturnType}; mod path; @@ -58,10 +62,9 @@ pub fn task(args: TokenStream, item: TokenStream) -> TokenStream { fail = true; } if pool_size < 1 { - Span::call_site() - .error("pool_size must be 1 or greater") - .emit(); - fail = true + return parse::Error::new(Span::call_site(), "pool_size must be 1 or greater") + .to_compile_error() + .into(); } let mut arg_names: syn::punctuated::Punctuated = @@ -120,6 +123,66 @@ pub fn task(args: TokenStream, item: TokenStream) -> TokenStream { result.into() } +#[proc_macro_attribute] +pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream { + let mut f: ItemFn = syn::parse(input).expect("`#[interrupt]` must be applied to a function"); + + if !args.is_empty() { + return parse::Error::new(Span::call_site(), "This attribute accepts no arguments") + .to_compile_error() + .into(); + } + + let fspan = f.span(); + let ident = f.sig.ident.clone(); + let ident_s = ident.to_string(); + + // XXX should we blacklist other attributes? + + let valid_signature = f.sig.constness.is_none() + && f.vis == Visibility::Inherited + && f.sig.abi.is_none() + && f.sig.inputs.is_empty() + && f.sig.generics.params.is_empty() + && f.sig.generics.where_clause.is_none() + && f.sig.variadic.is_none() + && match f.sig.output { + ReturnType::Default => true, + ReturnType::Type(_, ref ty) => match **ty { + Type::Tuple(ref tuple) => tuple.elems.is_empty(), + Type::Never(..) => true, + _ => false, + }, + }; + + if !valid_signature { + return parse::Error::new( + fspan, + "`#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`", + ) + .to_compile_error() + .into(); + } + + f.block.stmts = iter::once( + syn::parse2(quote! {{ + // Check that this interrupt actually exists + let __irq_exists_check: interrupt::#ident; + }}) + .unwrap(), + ) + .chain(f.block.stmts) + .collect(); + + quote!( + #[doc(hidden)] + #[export_name = #ident_s] + #[allow(non_snake_case)] + #f + ) + .into() +} + #[proc_macro] pub fn interrupt_declare(item: TokenStream) -> TokenStream { let name = syn::parse_macro_input!(item as syn::Ident); diff --git a/embassy-stm32-examples/Cargo.toml b/embassy-stm32-examples/Cargo.toml index 20f2af90..ab6fc6c1 100644 --- a/embassy-stm32-examples/Cargo.toml +++ b/embassy-stm32-examples/Cargo.toml @@ -20,7 +20,7 @@ embassy = { version = "0.1.0", path = "../embassy", features = ["defmt", "defmt- embassy-traits = { version = "0.1.0", path = "../embassy-traits", features = ["defmt"] } embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", features = ["defmt", "defmt-trace", "stm32f429zi"] } embassy-extras = {version = "0.1.0", path = "../embassy-extras" } -stm32f4 = { version = "0.13", features = ["stm32f429", "rt"] } +stm32f4 = { version = "0.13", features = ["stm32f429"] } defmt = "0.2.0" defmt-rtt = "0.2.0" diff --git a/embassy-stm32-examples/src/bin/blinky.rs b/embassy-stm32-examples/src/bin/blinky.rs index ec6c00fe..9ccd6c01 100644 --- a/embassy-stm32-examples/src/bin/blinky.rs +++ b/embassy-stm32-examples/src/bin/blinky.rs @@ -37,7 +37,8 @@ fn main() -> ! { w }); - let p = embassy_stm32::Peripherals::take().unwrap(); + let p = embassy_stm32::init(Default::default()); + let mut led = Output::new(p.PB7, Level::High); loop { diff --git a/embassy-stm32-examples/src/bin/button.rs b/embassy-stm32-examples/src/bin/button.rs index c02e34c0..c3421852 100644 --- a/embassy-stm32-examples/src/bin/button.rs +++ b/embassy-stm32-examples/src/bin/button.rs @@ -37,7 +37,8 @@ fn main() -> ! { w }); - let p = embassy_stm32::Peripherals::take().unwrap(); + let p = embassy_stm32::init(Default::default()); + let button = Input::new(p.PC13, Pull::Down); let mut led1 = Output::new(p.PB0, Level::High); let _led2 = Output::new(p.PB7, Level::High); diff --git a/embassy-stm32-examples/src/bin/button_exti.rs b/embassy-stm32-examples/src/bin/button_exti.rs index 8f679960..d6f545fa 100644 --- a/embassy-stm32-examples/src/bin/button_exti.rs +++ b/embassy-stm32-examples/src/bin/button_exti.rs @@ -16,12 +16,12 @@ use embassy_traits::gpio::{WaitForFallingEdge, WaitForRisingEdge}; use example_common::*; use cortex_m_rt::entry; -use pac::{interrupt, NVIC}; use stm32f4::stm32f429 as pac; #[embassy::task] async fn main_task() { - let p = embassy_stm32::Peripherals::take().unwrap(); + let p = embassy_stm32::init(Default::default()); + let button = Input::new(p.PC13, Pull::Down); let mut button = ExtiInput::new(button, p.EXTI13); @@ -74,56 +74,9 @@ fn main() -> ! { unsafe { embassy::time::set_clock(&ZeroClock) }; - unsafe { - NVIC::unmask(interrupt::EXTI0); - NVIC::unmask(interrupt::EXTI1); - NVIC::unmask(interrupt::EXTI2); - NVIC::unmask(interrupt::EXTI3); - NVIC::unmask(interrupt::EXTI4); - NVIC::unmask(interrupt::EXTI9_5); - NVIC::unmask(interrupt::EXTI15_10); - } - let executor = EXECUTOR.put(Executor::new()); executor.run(|spawner| { unwrap!(spawner.spawn(main_task())); }) } - -// TODO for now irq handling is done by user code using the old pac, until we figure out how interrupts work in the metapac - -#[interrupt] -unsafe fn EXTI0() { - exti::on_irq() -} - -#[interrupt] -unsafe fn EXTI1() { - exti::on_irq() -} - -#[interrupt] -unsafe fn EXTI2() { - exti::on_irq() -} - -#[interrupt] -unsafe fn EXTI3() { - exti::on_irq() -} - -#[interrupt] -unsafe fn EXTI4() { - exti::on_irq() -} - -#[interrupt] -unsafe fn EXTI9_5() { - exti::on_irq() -} - -#[interrupt] -unsafe fn EXTI15_10() { - exti::on_irq() -} diff --git a/embassy-stm32-examples/src/bin/usart.rs b/embassy-stm32-examples/src/bin/usart.rs index 02731c59..bf600831 100644 --- a/embassy-stm32-examples/src/bin/usart.rs +++ b/embassy-stm32-examples/src/bin/usart.rs @@ -15,12 +15,11 @@ use embassy_stm32::usart::{Config, Uart}; use example_common::*; use cortex_m_rt::entry; -use pac::{interrupt, NVIC}; use stm32f4::stm32f429 as pac; #[embassy::task] async fn main_task() { - let p = embassy_stm32::Peripherals::take().unwrap(); + let p = embassy_stm32::init(Default::default()); let config = Config::default(); let usart = Uart::new(p.USART3, p.PD9, p.PD8, NoPin, NoPin, config); @@ -61,10 +60,13 @@ fn main() -> ! { w }); pp.RCC.apb2enr.modify(|_, w| { - w.usart3en().enabled(); w.syscfgen().enabled(); w }); + pp.RCC.apb1enr.modify(|_, w| { + w.usart3en().enabled(); + w + }); unsafe { embassy::time::set_clock(&ZeroClock) }; diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index cfdec6f4..65943f2f 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -11,12 +11,15 @@ embassy-extras = {version = "0.1.0", path = "../embassy-extras" } defmt = { version = "0.2.0", optional = true } log = { version = "0.4.11", optional = true } -cortex-m-rt = "0.6.13" +cortex-m-rt = { version = "0.6.13", features = ["device"] } cortex-m = "0.7.1" embedded-hal = { version = "0.2.4" } futures = { version = "0.3.5", default-features = false, features = ["async-await"] } stm32-metapac = { path = "../../stm32-metapac"} +[build-dependencies] +regex = "1.4.6" + [features] defmt-trace = [ ] defmt-debug = [ ] diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs new file mode 100644 index 00000000..aacf4648 --- /dev/null +++ b/embassy-stm32/build.rs @@ -0,0 +1,34 @@ +use regex::Regex; +use std::fmt::Write as _; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +use std::{env, fs}; + +fn main() { + let chip = env::vars_os() + .map(|(a, _)| a.to_string_lossy().to_string()) + .find(|x| x.starts_with("CARGO_FEATURE_STM32")) + .expect("No stm32xx Cargo feature enabled") + .strip_prefix("CARGO_FEATURE_") + .unwrap() + .to_ascii_lowercase(); + + let mut device_x = String::new(); + + let chip_rs = fs::read_to_string(format!("src/chip/{}.rs", chip)).unwrap(); + let re = Regex::new("declare!\\(([a-zA-Z0-9_]+)\\)").unwrap(); + for c in re.captures_iter(&chip_rs) { + let name = c.get(1).unwrap().as_str(); + write!(&mut device_x, "PROVIDE({} = DefaultHandler);\n", name).unwrap(); + } + + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(device_x.as_bytes()) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=src/chip/{}.rs", chip); + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py index d1b8cd81..cf04cc15 100644 --- a/embassy-stm32/gen.py +++ b/embassy-stm32/gen.py @@ -90,7 +90,7 @@ for chip in chips.values(): if 'block' not in peri: continue - if peri['block'] == 'usart_v1/USART': + if peri['block'] in ('usart_v1/USART', 'usart_v1/UART'): impls.append(f'impl_usart!({name}, 0x{peri["address"]:x});') for pin, funcs in af.items(): if pin in pins: @@ -108,23 +108,67 @@ for chip in chips.values(): if peri['block'] == 'rng_v1/RNG': impls.append(f'impl_rng!(0x{peri["address"]:x});') - with open(f'src/chip/{chip["name"]}.rs', 'w') as f: - # TODO uart etc - # TODO import the right GPIO AF map mod - # TODO impl traits for the periperals + irq_variants = [] + irq_vectors = [] + irq_fns = [] + irq_declares = [] + irqs = {num: name for name, num in chip['interrupts'].items()} + irq_count = max(irqs.keys()) + 1 + for num, name in irqs.items(): + irq_variants.append(f'{name} = {num},') + irq_fns.append(f'fn {name}();') + irq_declares.append(f'declare!({name});') + for num in range(irq_count): + if name := irqs.get(num): + irq_vectors.append(f'Vector {{ _handler: {name} }},') + else: + irq_vectors.append(f'Vector {{ _reserved: 0 }},') + + with open(f'src/chip/{chip["name"]}.rs', 'w') as f: f.write(f""" - use embassy_extras::peripherals; - peripherals!({','.join(peripherals)}); - pub const GPIO_BASE: usize = 0x{gpio_base:x}; - pub const GPIO_STRIDE: usize = 0x{gpio_stride:x}; + use embassy_extras::peripherals; + peripherals!({','.join(peripherals)}); + pub const GPIO_BASE: usize = 0x{gpio_base:x}; + pub const GPIO_STRIDE: usize = 0x{gpio_stride:x}; + + pub mod interrupt {{ + pub use cortex_m::interrupt::{{CriticalSection, Mutex}}; + pub use embassy::interrupt::{{declare, take, Interrupt}}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum {{ + {''.join(irq_variants)} + }} + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {{ + #[inline(always)] + fn number(self) -> u16 {{ + self as u16 + }} + }} + + {''.join(irq_declares)} + }} + mod interrupt_vector {{ + extern "C" {{ + {''.join(irq_fns)} + }} + pub union Vector {{ + _handler: unsafe extern "C" fn(), + _reserved: u32, + }} + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; {irq_count}] = [ + {''.join(irq_vectors)} + ]; + }} """) for i in impls: f.write(i) -# TODO generate GPIO AF map mods - - # format os.system('rustfmt src/chip/*') diff --git a/embassy-stm32/src/chip/stm32f401cb.rs b/embassy-stm32/src/chip/stm32f401cb.rs index 2eeb68f3..654c39bd 100644 --- a/embassy-stm32/src/chip/stm32f401cb.rs +++ b/embassy-stm32/src/chip/stm32f401cb.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401cc.rs b/embassy-stm32/src/chip/stm32f401cc.rs index 2eeb68f3..654c39bd 100644 --- a/embassy-stm32/src/chip/stm32f401cc.rs +++ b/embassy-stm32/src/chip/stm32f401cc.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401cd.rs b/embassy-stm32/src/chip/stm32f401cd.rs index 2eeb68f3..654c39bd 100644 --- a/embassy-stm32/src/chip/stm32f401cd.rs +++ b/embassy-stm32/src/chip/stm32f401cd.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401ce.rs b/embassy-stm32/src/chip/stm32f401ce.rs index 2eeb68f3..654c39bd 100644 --- a/embassy-stm32/src/chip/stm32f401ce.rs +++ b/embassy-stm32/src/chip/stm32f401ce.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401rb.rs b/embassy-stm32/src/chip/stm32f401rb.rs index 1151263e..5c413734 100644 --- a/embassy-stm32/src/chip/stm32f401rb.rs +++ b/embassy-stm32/src/chip/stm32f401rb.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401rc.rs b/embassy-stm32/src/chip/stm32f401rc.rs index 1151263e..5c413734 100644 --- a/embassy-stm32/src/chip/stm32f401rc.rs +++ b/embassy-stm32/src/chip/stm32f401rc.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401rd.rs b/embassy-stm32/src/chip/stm32f401rd.rs index 1151263e..5c413734 100644 --- a/embassy-stm32/src/chip/stm32f401rd.rs +++ b/embassy-stm32/src/chip/stm32f401rd.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401re.rs b/embassy-stm32/src/chip/stm32f401re.rs index 1151263e..5c413734 100644 --- a/embassy-stm32/src/chip/stm32f401re.rs +++ b/embassy-stm32/src/chip/stm32f401re.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401vb.rs b/embassy-stm32/src/chip/stm32f401vb.rs index 1265de98..f9911116 100644 --- a/embassy-stm32/src/chip/stm32f401vb.rs +++ b/embassy-stm32/src/chip/stm32f401vb.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401vc.rs b/embassy-stm32/src/chip/stm32f401vc.rs index 1265de98..f9911116 100644 --- a/embassy-stm32/src/chip/stm32f401vc.rs +++ b/embassy-stm32/src/chip/stm32f401vc.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401vd.rs b/embassy-stm32/src/chip/stm32f401vd.rs index 1265de98..f9911116 100644 --- a/embassy-stm32/src/chip/stm32f401vd.rs +++ b/embassy-stm32/src/chip/stm32f401vd.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f401ve.rs b/embassy-stm32/src/chip/stm32f401ve.rs index 1265de98..f9911116 100644 --- a/embassy-stm32/src/chip/stm32f401ve.rs +++ b/embassy-stm32/src/chip/stm32f401ve.rs @@ -12,6 +12,335 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f405oe.rs b/embassy-stm32/src/chip/stm32f405oe.rs index 706b2af1..dcc229ce 100644 --- a/embassy-stm32/src/chip/stm32f405oe.rs +++ b/embassy-stm32/src/chip/stm32f405oe.rs @@ -16,6 +16,410 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f405og.rs b/embassy-stm32/src/chip/stm32f405og.rs index 706b2af1..dcc229ce 100644 --- a/embassy-stm32/src/chip/stm32f405og.rs +++ b/embassy-stm32/src/chip/stm32f405og.rs @@ -16,6 +16,410 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f405rg.rs b/embassy-stm32/src/chip/stm32f405rg.rs index 706b2af1..dcc229ce 100644 --- a/embassy-stm32/src/chip/stm32f405rg.rs +++ b/embassy-stm32/src/chip/stm32f405rg.rs @@ -16,6 +16,410 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f405vg.rs b/embassy-stm32/src/chip/stm32f405vg.rs index 706b2af1..dcc229ce 100644 --- a/embassy-stm32/src/chip/stm32f405vg.rs +++ b/embassy-stm32/src/chip/stm32f405vg.rs @@ -16,6 +16,410 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f405zg.rs b/embassy-stm32/src/chip/stm32f405zg.rs index 706b2af1..dcc229ce 100644 --- a/embassy-stm32/src/chip/stm32f405zg.rs +++ b/embassy-stm32/src/chip/stm32f405zg.rs @@ -16,6 +16,410 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f407ie.rs b/embassy-stm32/src/chip/stm32f407ie.rs index 48db7fa2..ac19c984 100644 --- a/embassy-stm32/src/chip/stm32f407ie.rs +++ b/embassy-stm32/src/chip/stm32f407ie.rs @@ -16,6 +16,419 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f407ig.rs b/embassy-stm32/src/chip/stm32f407ig.rs index 48db7fa2..ac19c984 100644 --- a/embassy-stm32/src/chip/stm32f407ig.rs +++ b/embassy-stm32/src/chip/stm32f407ig.rs @@ -16,6 +16,419 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f407ve.rs b/embassy-stm32/src/chip/stm32f407ve.rs index 48db7fa2..ac19c984 100644 --- a/embassy-stm32/src/chip/stm32f407ve.rs +++ b/embassy-stm32/src/chip/stm32f407ve.rs @@ -16,6 +16,419 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f407vg.rs b/embassy-stm32/src/chip/stm32f407vg.rs index 48db7fa2..ac19c984 100644 --- a/embassy-stm32/src/chip/stm32f407vg.rs +++ b/embassy-stm32/src/chip/stm32f407vg.rs @@ -16,6 +16,419 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f407ze.rs b/embassy-stm32/src/chip/stm32f407ze.rs index 48db7fa2..ac19c984 100644 --- a/embassy-stm32/src/chip/stm32f407ze.rs +++ b/embassy-stm32/src/chip/stm32f407ze.rs @@ -16,6 +16,419 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f407zg.rs b/embassy-stm32/src/chip/stm32f407zg.rs index 48db7fa2..ac19c984 100644 --- a/embassy-stm32/src/chip/stm32f407zg.rs +++ b/embassy-stm32/src/chip/stm32f407zg.rs @@ -16,6 +16,419 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f410c8.rs b/embassy-stm32/src/chip/stm32f410c8.rs index 400fd889..8015e97a 100644 --- a/embassy-stm32/src/chip/stm32f410c8.rs +++ b/embassy-stm32/src/chip/stm32f410c8.rs @@ -10,6 +10,336 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f410cb.rs b/embassy-stm32/src/chip/stm32f410cb.rs index 400fd889..8015e97a 100644 --- a/embassy-stm32/src/chip/stm32f410cb.rs +++ b/embassy-stm32/src/chip/stm32f410cb.rs @@ -10,6 +10,336 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f410r8.rs b/embassy-stm32/src/chip/stm32f410r8.rs index 400fd889..8015e97a 100644 --- a/embassy-stm32/src/chip/stm32f410r8.rs +++ b/embassy-stm32/src/chip/stm32f410r8.rs @@ -10,6 +10,336 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f410rb.rs b/embassy-stm32/src/chip/stm32f410rb.rs index 400fd889..8015e97a 100644 --- a/embassy-stm32/src/chip/stm32f410rb.rs +++ b/embassy-stm32/src/chip/stm32f410rb.rs @@ -10,6 +10,336 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f410t8.rs b/embassy-stm32/src/chip/stm32f410t8.rs index ec19c6d3..e3497384 100644 --- a/embassy-stm32/src/chip/stm32f410t8.rs +++ b/embassy-stm32/src/chip/stm32f410t8.rs @@ -10,6 +10,327 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f410tb.rs b/embassy-stm32/src/chip/stm32f410tb.rs index ec19c6d3..e3497384 100644 --- a/embassy-stm32/src/chip/stm32f410tb.rs +++ b/embassy-stm32/src/chip/stm32f410tb.rs @@ -10,6 +10,327 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f411cc.rs b/embassy-stm32/src/chip/stm32f411cc.rs index 5f90e3f4..5f0dbec6 100644 --- a/embassy-stm32/src/chip/stm32f411cc.rs +++ b/embassy-stm32/src/chip/stm32f411cc.rs @@ -12,6 +12,339 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f411ce.rs b/embassy-stm32/src/chip/stm32f411ce.rs index 5f90e3f4..5f0dbec6 100644 --- a/embassy-stm32/src/chip/stm32f411ce.rs +++ b/embassy-stm32/src/chip/stm32f411ce.rs @@ -12,6 +12,339 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f411rc.rs b/embassy-stm32/src/chip/stm32f411rc.rs index 5f90e3f4..5f0dbec6 100644 --- a/embassy-stm32/src/chip/stm32f411rc.rs +++ b/embassy-stm32/src/chip/stm32f411rc.rs @@ -12,6 +12,339 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f411re.rs b/embassy-stm32/src/chip/stm32f411re.rs index 5f90e3f4..5f0dbec6 100644 --- a/embassy-stm32/src/chip/stm32f411re.rs +++ b/embassy-stm32/src/chip/stm32f411re.rs @@ -12,6 +12,339 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f411vc.rs b/embassy-stm32/src/chip/stm32f411vc.rs index 5f90e3f4..5f0dbec6 100644 --- a/embassy-stm32/src/chip/stm32f411vc.rs +++ b/embassy-stm32/src/chip/stm32f411vc.rs @@ -12,6 +12,339 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f411ve.rs b/embassy-stm32/src/chip/stm32f411ve.rs index 5f90e3f4..5f0dbec6 100644 --- a/embassy-stm32/src/chip/stm32f411ve.rs +++ b/embassy-stm32/src/chip/stm32f411ve.rs @@ -12,6 +12,339 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f412ce.rs b/embassy-stm32/src/chip/stm32f412ce.rs index f2194552..f6749d13 100644 --- a/embassy-stm32/src/chip/stm32f412ce.rs +++ b/embassy-stm32/src/chip/stm32f412ce.rs @@ -11,6 +11,424 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f412cg.rs b/embassy-stm32/src/chip/stm32f412cg.rs index f2194552..f6749d13 100644 --- a/embassy-stm32/src/chip/stm32f412cg.rs +++ b/embassy-stm32/src/chip/stm32f412cg.rs @@ -11,6 +11,424 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f412re.rs b/embassy-stm32/src/chip/stm32f412re.rs index 60dafe05..4fda48d4 100644 --- a/embassy-stm32/src/chip/stm32f412re.rs +++ b/embassy-stm32/src/chip/stm32f412re.rs @@ -12,6 +12,427 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f412rg.rs b/embassy-stm32/src/chip/stm32f412rg.rs index 60dafe05..4fda48d4 100644 --- a/embassy-stm32/src/chip/stm32f412rg.rs +++ b/embassy-stm32/src/chip/stm32f412rg.rs @@ -12,6 +12,427 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f412ve.rs b/embassy-stm32/src/chip/stm32f412ve.rs index c405a041..798ca7f4 100644 --- a/embassy-stm32/src/chip/stm32f412ve.rs +++ b/embassy-stm32/src/chip/stm32f412ve.rs @@ -15,6 +15,427 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f412vg.rs b/embassy-stm32/src/chip/stm32f412vg.rs index c405a041..798ca7f4 100644 --- a/embassy-stm32/src/chip/stm32f412vg.rs +++ b/embassy-stm32/src/chip/stm32f412vg.rs @@ -15,6 +15,427 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f412ze.rs b/embassy-stm32/src/chip/stm32f412ze.rs index c405a041..798ca7f4 100644 --- a/embassy-stm32/src/chip/stm32f412ze.rs +++ b/embassy-stm32/src/chip/stm32f412ze.rs @@ -15,6 +15,427 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f412zg.rs b/embassy-stm32/src/chip/stm32f412zg.rs index c405a041..798ca7f4 100644 --- a/embassy-stm32/src/chip/stm32f412zg.rs +++ b/embassy-stm32/src/chip/stm32f412zg.rs @@ -15,6 +15,427 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413cg.rs b/embassy-stm32/src/chip/stm32f413cg.rs index 557723e9..485fce7b 100644 --- a/embassy-stm32/src/chip/stm32f413cg.rs +++ b/embassy-stm32/src/chip/stm32f413cg.rs @@ -15,6 +15,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413ch.rs b/embassy-stm32/src/chip/stm32f413ch.rs index 557723e9..485fce7b 100644 --- a/embassy-stm32/src/chip/stm32f413ch.rs +++ b/embassy-stm32/src/chip/stm32f413ch.rs @@ -15,6 +15,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413mg.rs b/embassy-stm32/src/chip/stm32f413mg.rs index 009e1e87..d0a83492 100644 --- a/embassy-stm32/src/chip/stm32f413mg.rs +++ b/embassy-stm32/src/chip/stm32f413mg.rs @@ -15,6 +15,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413mh.rs b/embassy-stm32/src/chip/stm32f413mh.rs index 009e1e87..d0a83492 100644 --- a/embassy-stm32/src/chip/stm32f413mh.rs +++ b/embassy-stm32/src/chip/stm32f413mh.rs @@ -15,6 +15,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413rg.rs b/embassy-stm32/src/chip/stm32f413rg.rs index 009e1e87..d0a83492 100644 --- a/embassy-stm32/src/chip/stm32f413rg.rs +++ b/embassy-stm32/src/chip/stm32f413rg.rs @@ -15,6 +15,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413rh.rs b/embassy-stm32/src/chip/stm32f413rh.rs index 009e1e87..d0a83492 100644 --- a/embassy-stm32/src/chip/stm32f413rh.rs +++ b/embassy-stm32/src/chip/stm32f413rh.rs @@ -15,6 +15,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413vg.rs b/embassy-stm32/src/chip/stm32f413vg.rs index 1212322e..e2d6a981 100644 --- a/embassy-stm32/src/chip/stm32f413vg.rs +++ b/embassy-stm32/src/chip/stm32f413vg.rs @@ -16,6 +16,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413vh.rs b/embassy-stm32/src/chip/stm32f413vh.rs index 1212322e..e2d6a981 100644 --- a/embassy-stm32/src/chip/stm32f413vh.rs +++ b/embassy-stm32/src/chip/stm32f413vh.rs @@ -16,6 +16,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413zg.rs b/embassy-stm32/src/chip/stm32f413zg.rs index 1212322e..e2d6a981 100644 --- a/embassy-stm32/src/chip/stm32f413zg.rs +++ b/embassy-stm32/src/chip/stm32f413zg.rs @@ -16,6 +16,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f413zh.rs b/embassy-stm32/src/chip/stm32f413zh.rs index 1212322e..e2d6a981 100644 --- a/embassy-stm32/src/chip/stm32f413zh.rs +++ b/embassy-stm32/src/chip/stm32f413zh.rs @@ -16,6 +16,488 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f415og.rs b/embassy-stm32/src/chip/stm32f415og.rs index 919e2a64..cd801d6c 100644 --- a/embassy-stm32/src/chip/stm32f415og.rs +++ b/embassy-stm32/src/chip/stm32f415og.rs @@ -16,6 +16,413 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f415rg.rs b/embassy-stm32/src/chip/stm32f415rg.rs index 919e2a64..cd801d6c 100644 --- a/embassy-stm32/src/chip/stm32f415rg.rs +++ b/embassy-stm32/src/chip/stm32f415rg.rs @@ -16,6 +16,413 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f415vg.rs b/embassy-stm32/src/chip/stm32f415vg.rs index 919e2a64..cd801d6c 100644 --- a/embassy-stm32/src/chip/stm32f415vg.rs +++ b/embassy-stm32/src/chip/stm32f415vg.rs @@ -16,6 +16,413 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f415zg.rs b/embassy-stm32/src/chip/stm32f415zg.rs index 919e2a64..cd801d6c 100644 --- a/embassy-stm32/src/chip/stm32f415zg.rs +++ b/embassy-stm32/src/chip/stm32f415zg.rs @@ -16,6 +16,413 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f417ie.rs b/embassy-stm32/src/chip/stm32f417ie.rs index 56d3778c..03454307 100644 --- a/embassy-stm32/src/chip/stm32f417ie.rs +++ b/embassy-stm32/src/chip/stm32f417ie.rs @@ -16,6 +16,422 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f417ig.rs b/embassy-stm32/src/chip/stm32f417ig.rs index 56d3778c..03454307 100644 --- a/embassy-stm32/src/chip/stm32f417ig.rs +++ b/embassy-stm32/src/chip/stm32f417ig.rs @@ -16,6 +16,422 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f417ve.rs b/embassy-stm32/src/chip/stm32f417ve.rs index 56d3778c..03454307 100644 --- a/embassy-stm32/src/chip/stm32f417ve.rs +++ b/embassy-stm32/src/chip/stm32f417ve.rs @@ -16,6 +16,422 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f417vg.rs b/embassy-stm32/src/chip/stm32f417vg.rs index 56d3778c..03454307 100644 --- a/embassy-stm32/src/chip/stm32f417vg.rs +++ b/embassy-stm32/src/chip/stm32f417vg.rs @@ -16,6 +16,422 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f417ze.rs b/embassy-stm32/src/chip/stm32f417ze.rs index 56d3778c..03454307 100644 --- a/embassy-stm32/src/chip/stm32f417ze.rs +++ b/embassy-stm32/src/chip/stm32f417ze.rs @@ -16,6 +16,422 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f417zg.rs b/embassy-stm32/src/chip/stm32f417zg.rs index 56d3778c..03454307 100644 --- a/embassy-stm32/src/chip/stm32f417zg.rs +++ b/embassy-stm32/src/chip/stm32f417zg.rs @@ -16,6 +16,422 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f423ch.rs b/embassy-stm32/src/chip/stm32f423ch.rs index 4b4d17e0..ddb9ee0f 100644 --- a/embassy-stm32/src/chip/stm32f423ch.rs +++ b/embassy-stm32/src/chip/stm32f423ch.rs @@ -15,6 +15,491 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f423mh.rs b/embassy-stm32/src/chip/stm32f423mh.rs index 2da87958..adedcbc2 100644 --- a/embassy-stm32/src/chip/stm32f423mh.rs +++ b/embassy-stm32/src/chip/stm32f423mh.rs @@ -15,6 +15,491 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f423rh.rs b/embassy-stm32/src/chip/stm32f423rh.rs index 2da87958..adedcbc2 100644 --- a/embassy-stm32/src/chip/stm32f423rh.rs +++ b/embassy-stm32/src/chip/stm32f423rh.rs @@ -15,6 +15,491 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f423vh.rs b/embassy-stm32/src/chip/stm32f423vh.rs index bbe4c056..6c531d7f 100644 --- a/embassy-stm32/src/chip/stm32f423vh.rs +++ b/embassy-stm32/src/chip/stm32f423vh.rs @@ -16,6 +16,491 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f423zh.rs b/embassy-stm32/src/chip/stm32f423zh.rs index bbe4c056..6c531d7f 100644 --- a/embassy-stm32/src/chip/stm32f423zh.rs +++ b/embassy-stm32/src/chip/stm32f423zh.rs @@ -16,6 +16,491 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f427ag.rs b/embassy-stm32/src/chip/stm32f427ag.rs index 2511085a..0251a0bc 100644 --- a/embassy-stm32/src/chip/stm32f427ag.rs +++ b/embassy-stm32/src/chip/stm32f427ag.rs @@ -18,6 +18,449 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f427ai.rs b/embassy-stm32/src/chip/stm32f427ai.rs index 2511085a..0251a0bc 100644 --- a/embassy-stm32/src/chip/stm32f427ai.rs +++ b/embassy-stm32/src/chip/stm32f427ai.rs @@ -18,6 +18,449 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f427ig.rs b/embassy-stm32/src/chip/stm32f427ig.rs index 9eebdc8e..9111a78c 100644 --- a/embassy-stm32/src/chip/stm32f427ig.rs +++ b/embassy-stm32/src/chip/stm32f427ig.rs @@ -18,6 +18,449 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f427ii.rs b/embassy-stm32/src/chip/stm32f427ii.rs index 9eebdc8e..9111a78c 100644 --- a/embassy-stm32/src/chip/stm32f427ii.rs +++ b/embassy-stm32/src/chip/stm32f427ii.rs @@ -18,6 +18,449 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f427vg.rs b/embassy-stm32/src/chip/stm32f427vg.rs index 42dd8dee..fdebb3b9 100644 --- a/embassy-stm32/src/chip/stm32f427vg.rs +++ b/embassy-stm32/src/chip/stm32f427vg.rs @@ -18,6 +18,449 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f427vi.rs b/embassy-stm32/src/chip/stm32f427vi.rs index 42dd8dee..fdebb3b9 100644 --- a/embassy-stm32/src/chip/stm32f427vi.rs +++ b/embassy-stm32/src/chip/stm32f427vi.rs @@ -18,6 +18,449 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f427zg.rs b/embassy-stm32/src/chip/stm32f427zg.rs index 9eebdc8e..9111a78c 100644 --- a/embassy-stm32/src/chip/stm32f427zg.rs +++ b/embassy-stm32/src/chip/stm32f427zg.rs @@ -18,6 +18,449 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f427zi.rs b/embassy-stm32/src/chip/stm32f427zi.rs index 9eebdc8e..9111a78c 100644 --- a/embassy-stm32/src/chip/stm32f427zi.rs +++ b/embassy-stm32/src/chip/stm32f427zi.rs @@ -18,6 +18,449 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ag.rs b/embassy-stm32/src/chip/stm32f429ag.rs index 0cd1fabb..40865585 100644 --- a/embassy-stm32/src/chip/stm32f429ag.rs +++ b/embassy-stm32/src/chip/stm32f429ag.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ai.rs b/embassy-stm32/src/chip/stm32f429ai.rs index 0cd1fabb..40865585 100644 --- a/embassy-stm32/src/chip/stm32f429ai.rs +++ b/embassy-stm32/src/chip/stm32f429ai.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429be.rs b/embassy-stm32/src/chip/stm32f429be.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429be.rs +++ b/embassy-stm32/src/chip/stm32f429be.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429bg.rs b/embassy-stm32/src/chip/stm32f429bg.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429bg.rs +++ b/embassy-stm32/src/chip/stm32f429bg.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429bi.rs b/embassy-stm32/src/chip/stm32f429bi.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429bi.rs +++ b/embassy-stm32/src/chip/stm32f429bi.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ie.rs b/embassy-stm32/src/chip/stm32f429ie.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429ie.rs +++ b/embassy-stm32/src/chip/stm32f429ie.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ig.rs b/embassy-stm32/src/chip/stm32f429ig.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429ig.rs +++ b/embassy-stm32/src/chip/stm32f429ig.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ii.rs b/embassy-stm32/src/chip/stm32f429ii.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429ii.rs +++ b/embassy-stm32/src/chip/stm32f429ii.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ne.rs b/embassy-stm32/src/chip/stm32f429ne.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429ne.rs +++ b/embassy-stm32/src/chip/stm32f429ne.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ng.rs b/embassy-stm32/src/chip/stm32f429ng.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429ng.rs +++ b/embassy-stm32/src/chip/stm32f429ng.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ni.rs b/embassy-stm32/src/chip/stm32f429ni.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429ni.rs +++ b/embassy-stm32/src/chip/stm32f429ni.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ve.rs b/embassy-stm32/src/chip/stm32f429ve.rs index 1a9a3eed..f9532b2d 100644 --- a/embassy-stm32/src/chip/stm32f429ve.rs +++ b/embassy-stm32/src/chip/stm32f429ve.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429vg.rs b/embassy-stm32/src/chip/stm32f429vg.rs index 1a9a3eed..f9532b2d 100644 --- a/embassy-stm32/src/chip/stm32f429vg.rs +++ b/embassy-stm32/src/chip/stm32f429vg.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429vi.rs b/embassy-stm32/src/chip/stm32f429vi.rs index 1a9a3eed..f9532b2d 100644 --- a/embassy-stm32/src/chip/stm32f429vi.rs +++ b/embassy-stm32/src/chip/stm32f429vi.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429ze.rs b/embassy-stm32/src/chip/stm32f429ze.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429ze.rs +++ b/embassy-stm32/src/chip/stm32f429ze.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429zg.rs b/embassy-stm32/src/chip/stm32f429zg.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429zg.rs +++ b/embassy-stm32/src/chip/stm32f429zg.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f429zi.rs b/embassy-stm32/src/chip/stm32f429zi.rs index 5a7ac0a6..1a285e03 100644 --- a/embassy-stm32/src/chip/stm32f429zi.rs +++ b/embassy-stm32/src/chip/stm32f429zi.rs @@ -18,6 +18,455 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f437ai.rs b/embassy-stm32/src/chip/stm32f437ai.rs index 6960fb24..14d3863e 100644 --- a/embassy-stm32/src/chip/stm32f437ai.rs +++ b/embassy-stm32/src/chip/stm32f437ai.rs @@ -18,6 +18,452 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f437ig.rs b/embassy-stm32/src/chip/stm32f437ig.rs index 309b14e0..e7eec4f5 100644 --- a/embassy-stm32/src/chip/stm32f437ig.rs +++ b/embassy-stm32/src/chip/stm32f437ig.rs @@ -18,6 +18,452 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f437ii.rs b/embassy-stm32/src/chip/stm32f437ii.rs index 309b14e0..e7eec4f5 100644 --- a/embassy-stm32/src/chip/stm32f437ii.rs +++ b/embassy-stm32/src/chip/stm32f437ii.rs @@ -18,6 +18,452 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f437vg.rs b/embassy-stm32/src/chip/stm32f437vg.rs index d6b80875..a570e960 100644 --- a/embassy-stm32/src/chip/stm32f437vg.rs +++ b/embassy-stm32/src/chip/stm32f437vg.rs @@ -18,6 +18,452 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f437vi.rs b/embassy-stm32/src/chip/stm32f437vi.rs index d6b80875..a570e960 100644 --- a/embassy-stm32/src/chip/stm32f437vi.rs +++ b/embassy-stm32/src/chip/stm32f437vi.rs @@ -18,6 +18,452 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f437zg.rs b/embassy-stm32/src/chip/stm32f437zg.rs index 309b14e0..e7eec4f5 100644 --- a/embassy-stm32/src/chip/stm32f437zg.rs +++ b/embassy-stm32/src/chip/stm32f437zg.rs @@ -18,6 +18,452 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f437zi.rs b/embassy-stm32/src/chip/stm32f437zi.rs index 309b14e0..e7eec4f5 100644 --- a/embassy-stm32/src/chip/stm32f437zi.rs +++ b/embassy-stm32/src/chip/stm32f437zi.rs @@ -18,6 +18,452 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439ai.rs b/embassy-stm32/src/chip/stm32f439ai.rs index 16621b67..6475617f 100644 --- a/embassy-stm32/src/chip/stm32f439ai.rs +++ b/embassy-stm32/src/chip/stm32f439ai.rs @@ -18,6 +18,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439bg.rs b/embassy-stm32/src/chip/stm32f439bg.rs index d384f3da..11fbc8ad 100644 --- a/embassy-stm32/src/chip/stm32f439bg.rs +++ b/embassy-stm32/src/chip/stm32f439bg.rs @@ -19,6 +19,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439bi.rs b/embassy-stm32/src/chip/stm32f439bi.rs index d384f3da..11fbc8ad 100644 --- a/embassy-stm32/src/chip/stm32f439bi.rs +++ b/embassy-stm32/src/chip/stm32f439bi.rs @@ -19,6 +19,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439ig.rs b/embassy-stm32/src/chip/stm32f439ig.rs index d384f3da..11fbc8ad 100644 --- a/embassy-stm32/src/chip/stm32f439ig.rs +++ b/embassy-stm32/src/chip/stm32f439ig.rs @@ -19,6 +19,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439ii.rs b/embassy-stm32/src/chip/stm32f439ii.rs index d384f3da..11fbc8ad 100644 --- a/embassy-stm32/src/chip/stm32f439ii.rs +++ b/embassy-stm32/src/chip/stm32f439ii.rs @@ -19,6 +19,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439ng.rs b/embassy-stm32/src/chip/stm32f439ng.rs index d384f3da..11fbc8ad 100644 --- a/embassy-stm32/src/chip/stm32f439ng.rs +++ b/embassy-stm32/src/chip/stm32f439ng.rs @@ -19,6 +19,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439ni.rs b/embassy-stm32/src/chip/stm32f439ni.rs index d384f3da..11fbc8ad 100644 --- a/embassy-stm32/src/chip/stm32f439ni.rs +++ b/embassy-stm32/src/chip/stm32f439ni.rs @@ -19,6 +19,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439vg.rs b/embassy-stm32/src/chip/stm32f439vg.rs index 604ae003..b195f3ac 100644 --- a/embassy-stm32/src/chip/stm32f439vg.rs +++ b/embassy-stm32/src/chip/stm32f439vg.rs @@ -18,6 +18,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439vi.rs b/embassy-stm32/src/chip/stm32f439vi.rs index 604ae003..b195f3ac 100644 --- a/embassy-stm32/src/chip/stm32f439vi.rs +++ b/embassy-stm32/src/chip/stm32f439vi.rs @@ -18,6 +18,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439zg.rs b/embassy-stm32/src/chip/stm32f439zg.rs index d384f3da..11fbc8ad 100644 --- a/embassy-stm32/src/chip/stm32f439zg.rs +++ b/embassy-stm32/src/chip/stm32f439zg.rs @@ -19,6 +19,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f439zi.rs b/embassy-stm32/src/chip/stm32f439zi.rs index d384f3da..11fbc8ad 100644 --- a/embassy-stm32/src/chip/stm32f439zi.rs +++ b/embassy-stm32/src/chip/stm32f439zi.rs @@ -19,6 +19,458 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f446mc.rs b/embassy-stm32/src/chip/stm32f446mc.rs index ea3cecb7..acf4a396 100644 --- a/embassy-stm32/src/chip/stm32f446mc.rs +++ b/embassy-stm32/src/chip/stm32f446mc.rs @@ -15,6 +15,453 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f446me.rs b/embassy-stm32/src/chip/stm32f446me.rs index ea3cecb7..acf4a396 100644 --- a/embassy-stm32/src/chip/stm32f446me.rs +++ b/embassy-stm32/src/chip/stm32f446me.rs @@ -15,6 +15,453 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f446rc.rs b/embassy-stm32/src/chip/stm32f446rc.rs index 6898d0fc..6392b768 100644 --- a/embassy-stm32/src/chip/stm32f446rc.rs +++ b/embassy-stm32/src/chip/stm32f446rc.rs @@ -15,6 +15,453 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f446re.rs b/embassy-stm32/src/chip/stm32f446re.rs index 6898d0fc..6392b768 100644 --- a/embassy-stm32/src/chip/stm32f446re.rs +++ b/embassy-stm32/src/chip/stm32f446re.rs @@ -15,6 +15,453 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f446vc.rs b/embassy-stm32/src/chip/stm32f446vc.rs index ea3cecb7..acf4a396 100644 --- a/embassy-stm32/src/chip/stm32f446vc.rs +++ b/embassy-stm32/src/chip/stm32f446vc.rs @@ -15,6 +15,453 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f446ve.rs b/embassy-stm32/src/chip/stm32f446ve.rs index ea3cecb7..acf4a396 100644 --- a/embassy-stm32/src/chip/stm32f446ve.rs +++ b/embassy-stm32/src/chip/stm32f446ve.rs @@ -15,6 +15,453 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f446zc.rs b/embassy-stm32/src/chip/stm32f446zc.rs index ea3cecb7..acf4a396 100644 --- a/embassy-stm32/src/chip/stm32f446zc.rs +++ b/embassy-stm32/src/chip/stm32f446zc.rs @@ -15,6 +15,453 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f446ze.rs b/embassy-stm32/src/chip/stm32f446ze.rs index ea3cecb7..acf4a396 100644 --- a/embassy-stm32/src/chip/stm32f446ze.rs +++ b/embassy-stm32/src/chip/stm32f446ze.rs @@ -15,6 +15,453 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ae.rs b/embassy-stm32/src/chip/stm32f469ae.rs index 33832098..a9503f67 100644 --- a/embassy-stm32/src/chip/stm32f469ae.rs +++ b/embassy-stm32/src/chip/stm32f469ae.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ag.rs b/embassy-stm32/src/chip/stm32f469ag.rs index 33832098..a9503f67 100644 --- a/embassy-stm32/src/chip/stm32f469ag.rs +++ b/embassy-stm32/src/chip/stm32f469ag.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ai.rs b/embassy-stm32/src/chip/stm32f469ai.rs index 33832098..a9503f67 100644 --- a/embassy-stm32/src/chip/stm32f469ai.rs +++ b/embassy-stm32/src/chip/stm32f469ai.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469be.rs b/embassy-stm32/src/chip/stm32f469be.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469be.rs +++ b/embassy-stm32/src/chip/stm32f469be.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469bg.rs b/embassy-stm32/src/chip/stm32f469bg.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469bg.rs +++ b/embassy-stm32/src/chip/stm32f469bg.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469bi.rs b/embassy-stm32/src/chip/stm32f469bi.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469bi.rs +++ b/embassy-stm32/src/chip/stm32f469bi.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ie.rs b/embassy-stm32/src/chip/stm32f469ie.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469ie.rs +++ b/embassy-stm32/src/chip/stm32f469ie.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ig.rs b/embassy-stm32/src/chip/stm32f469ig.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469ig.rs +++ b/embassy-stm32/src/chip/stm32f469ig.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ii.rs b/embassy-stm32/src/chip/stm32f469ii.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469ii.rs +++ b/embassy-stm32/src/chip/stm32f469ii.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ne.rs b/embassy-stm32/src/chip/stm32f469ne.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469ne.rs +++ b/embassy-stm32/src/chip/stm32f469ne.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ng.rs b/embassy-stm32/src/chip/stm32f469ng.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469ng.rs +++ b/embassy-stm32/src/chip/stm32f469ng.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ni.rs b/embassy-stm32/src/chip/stm32f469ni.rs index 73484061..53bd9fd9 100644 --- a/embassy-stm32/src/chip/stm32f469ni.rs +++ b/embassy-stm32/src/chip/stm32f469ni.rs @@ -19,6 +19,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ve.rs b/embassy-stm32/src/chip/stm32f469ve.rs index f11c35a0..0d2dc9c9 100644 --- a/embassy-stm32/src/chip/stm32f469ve.rs +++ b/embassy-stm32/src/chip/stm32f469ve.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469vg.rs b/embassy-stm32/src/chip/stm32f469vg.rs index f11c35a0..0d2dc9c9 100644 --- a/embassy-stm32/src/chip/stm32f469vg.rs +++ b/embassy-stm32/src/chip/stm32f469vg.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469vi.rs b/embassy-stm32/src/chip/stm32f469vi.rs index f11c35a0..0d2dc9c9 100644 --- a/embassy-stm32/src/chip/stm32f469vi.rs +++ b/embassy-stm32/src/chip/stm32f469vi.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469ze.rs b/embassy-stm32/src/chip/stm32f469ze.rs index 8c8d412b..aaeefbeb 100644 --- a/embassy-stm32/src/chip/stm32f469ze.rs +++ b/embassy-stm32/src/chip/stm32f469ze.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469zg.rs b/embassy-stm32/src/chip/stm32f469zg.rs index 8c8d412b..aaeefbeb 100644 --- a/embassy-stm32/src/chip/stm32f469zg.rs +++ b/embassy-stm32/src/chip/stm32f469zg.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f469zi.rs b/embassy-stm32/src/chip/stm32f469zi.rs index 8c8d412b..aaeefbeb 100644 --- a/embassy-stm32/src/chip/stm32f469zi.rs +++ b/embassy-stm32/src/chip/stm32f469zi.rs @@ -18,6 +18,463 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479ag.rs b/embassy-stm32/src/chip/stm32f479ag.rs index 89b9e538..110026c8 100644 --- a/embassy-stm32/src/chip/stm32f479ag.rs +++ b/embassy-stm32/src/chip/stm32f479ag.rs @@ -19,6 +19,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479ai.rs b/embassy-stm32/src/chip/stm32f479ai.rs index 89b9e538..110026c8 100644 --- a/embassy-stm32/src/chip/stm32f479ai.rs +++ b/embassy-stm32/src/chip/stm32f479ai.rs @@ -19,6 +19,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479bg.rs b/embassy-stm32/src/chip/stm32f479bg.rs index 55b7542b..d5133d31 100644 --- a/embassy-stm32/src/chip/stm32f479bg.rs +++ b/embassy-stm32/src/chip/stm32f479bg.rs @@ -19,6 +19,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479bi.rs b/embassy-stm32/src/chip/stm32f479bi.rs index 55b7542b..d5133d31 100644 --- a/embassy-stm32/src/chip/stm32f479bi.rs +++ b/embassy-stm32/src/chip/stm32f479bi.rs @@ -19,6 +19,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479ig.rs b/embassy-stm32/src/chip/stm32f479ig.rs index 55b7542b..d5133d31 100644 --- a/embassy-stm32/src/chip/stm32f479ig.rs +++ b/embassy-stm32/src/chip/stm32f479ig.rs @@ -19,6 +19,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479ii.rs b/embassy-stm32/src/chip/stm32f479ii.rs index 55b7542b..d5133d31 100644 --- a/embassy-stm32/src/chip/stm32f479ii.rs +++ b/embassy-stm32/src/chip/stm32f479ii.rs @@ -19,6 +19,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479ng.rs b/embassy-stm32/src/chip/stm32f479ng.rs index 55b7542b..d5133d31 100644 --- a/embassy-stm32/src/chip/stm32f479ng.rs +++ b/embassy-stm32/src/chip/stm32f479ng.rs @@ -19,6 +19,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479ni.rs b/embassy-stm32/src/chip/stm32f479ni.rs index 55b7542b..d5133d31 100644 --- a/embassy-stm32/src/chip/stm32f479ni.rs +++ b/embassy-stm32/src/chip/stm32f479ni.rs @@ -19,6 +19,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479vg.rs b/embassy-stm32/src/chip/stm32f479vg.rs index 365bd1ed..d5f37360 100644 --- a/embassy-stm32/src/chip/stm32f479vg.rs +++ b/embassy-stm32/src/chip/stm32f479vg.rs @@ -18,6 +18,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479vi.rs b/embassy-stm32/src/chip/stm32f479vi.rs index 365bd1ed..d5f37360 100644 --- a/embassy-stm32/src/chip/stm32f479vi.rs +++ b/embassy-stm32/src/chip/stm32f479vi.rs @@ -18,6 +18,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479zg.rs b/embassy-stm32/src/chip/stm32f479zg.rs index 2bebe947..76134afa 100644 --- a/embassy-stm32/src/chip/stm32f479zg.rs +++ b/embassy-stm32/src/chip/stm32f479zg.rs @@ -18,6 +18,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/chip/stm32f479zi.rs b/embassy-stm32/src/chip/stm32f479zi.rs index 2bebe947..76134afa 100644 --- a/embassy-stm32/src/chip/stm32f479zi.rs +++ b/embassy-stm32/src/chip/stm32f479zi.rs @@ -18,6 +18,466 @@ peripherals!( ); pub const GPIO_BASE: usize = 0x40020000; pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} impl_gpio_pin!(PA0, 0, 0, EXTI0); impl_gpio_pin!(PA1, 0, 1, EXTI1); impl_gpio_pin!(PA2, 0, 2, EXTI2); diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs index d1b5eabb..c952dccb 100644 --- a/embassy-stm32/src/exti.rs +++ b/embassy-stm32/src/exti.rs @@ -7,11 +7,11 @@ use embassy::traits::gpio::{WaitForAnyEdge, WaitForFallingEdge, WaitForRisingEdg use embassy::util::{AtomicWaker, Unborrow}; use embassy_extras::impl_unborrow; use embedded_hal::digital::v2::InputPin; -use futures::future::Select; use pac::exti::{regs, vals}; use crate::fmt::*; use crate::gpio::{AnyPin, Input, Pin as GpioPin}; +use crate::interrupt; use crate::pac; use crate::peripherals; @@ -23,7 +23,41 @@ const EXTI_COUNT: usize = 16; const NEW_AW: AtomicWaker = AtomicWaker::new(); static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [NEW_AW; EXTI_COUNT]; -// TODO for now delegate irq handling to user code until we figure out how interrupts work in the metapac +#[interrupt] +unsafe fn EXTI0() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI1() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI2() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI3() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI4() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI9_5() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI15_10() { + on_irq() +} + pub unsafe fn on_irq() { let bits = EXTI.pr().read().0; diff --git a/embassy-stm32/src/interrupt.rs b/embassy-stm32/src/interrupt.rs index 63b80a6c..21432730 100644 --- a/embassy-stm32/src/interrupt.rs +++ b/embassy-stm32/src/interrupt.rs @@ -1,8 +1,3 @@ -//! Interrupt management -//! -//! This module implements an API for managing interrupts compatible with -//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time. - use core::sync::atomic::{compiler_fence, Ordering}; use crate::pac::NVIC_PRIO_BITS; @@ -62,1066 +57,3 @@ impl From for u8 { (p as u8) << (8 - NVIC_PRIO_BITS) } } - -#[inline] -pub fn free(f: F) -> R -where - F: FnOnce(&CriticalSection) -> R, -{ - unsafe { - // TODO: assert that we're in privileged level - // Needed because disabling irqs in non-privileged level is a noop, which would break safety. - - let primask: u32; - asm!("mrs {}, PRIMASK", out(reg) primask); - - asm!("cpsid i"); - - // Prevent compiler from reordering operations inside/outside the critical section. - compiler_fence(Ordering::SeqCst); - - let r = f(&CriticalSection::new()); - - compiler_fence(Ordering::SeqCst); - - if primask & 1 == 0 { - asm!("cpsie i"); - } - - r - } -} - -#[cfg(feature = "stm32f401")] -mod irqs { - use super::*; - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(DMA1_STREAM7); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(FPU); - declare!(SPI4); -} - -#[cfg(feature = "stm32f405")] -mod irqs { - use super::*; - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - // declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - // declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - // declare!(UART7); - // declare!(UART8); - // declare!(SPI4); - // declare!(SPI5); - // declare!(SPI6); - // declare!(SAI1); - // declare!(LCD_TFT); - // declare!(LCD_TFT_1); - // declare!(DMA2D); -} - -#[cfg(feature = "stm32f407")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FSMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - declare!(LCD_TFT); - declare!(LCD_TFT_1); -} - -#[cfg(feature = "stm32f410")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(PWM1_UP); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(DMA1_STREAM7); - declare!(TIM5); - declare!(TIM6_DAC1); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(EXTI19); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(EXTI20); - declare!(RNG); - declare!(FPU); - declare!(SPI5); - declare!(I2C4_EV); - declare!(I2C4_ER); - declare!(LPTIM1); -} - -#[cfg(feature = "stm32f411")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(DMA1_STREAM7); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(FPU); - declare!(SPI4); - declare!(SPI5); -} - -#[cfg(feature = "stm32f412")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM12); - declare!(TIM13); - declare!(TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FSMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(TIM6_DACUNDER); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(HASH_RNG); - declare!(FPU); - declare!(SPI4); - declare!(SPI5); - declare!(QUAD_SPI); - declare!(I2CFMP1_EVENT); - declare!(I2CFMP1_ERROR); -} - -#[cfg(feature = "stm32f413")] -mod irqs { - use super::*; - - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EVT); - declare!(I2C1_ERR); - declare!(I2C2_EVT); - declare!(I2C2_ERR); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(EXTI17_RTC_ALARM); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FSMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(USART4); - declare!(UART5); - declare!(TIM6_GLB_IT_DAC1_DAC2); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(DFSDM1_FLT0); - declare!(DFSDM1_FLT1); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(CAN3_TX); - declare!(CAN3_RX0); - declare!(CAN3_RX1); - declare!(CAN3_SCE); - declare!(CRYPTO); - declare!(RNG); - declare!(FPU); - declare!(USART7); - declare!(USART8); - declare!(SPI4); - declare!(SPI5); - declare!(SAI1); - declare!(UART9); - declare!(UART10); - declare!(QUADSPI); - declare!(I2CFMP1EVENT); - declare!(I2CFMP1ERROR); - declare!(LPTIM1_OR_IT_EIT_23); - declare!(DFSDM2_FILTER1); - declare!(DFSDM2_FILTER2); - declare!(DFSDM2_FILTER3); - declare!(DFSDM2_FILTER4); -} - -#[cfg(feature = "stm32f427")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - declare!(UART7); - declare!(UART8); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(LCD_TFT); - declare!(LCD_TFT_1); -} - -#[cfg(feature = "stm32f429")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - declare!(UART7); - declare!(UART8); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(SAI1); - declare!(LCD_TFT); - declare!(LCD_TFT_1); - declare!(DMA2D); -} - -#[cfg(feature = "stm32f446")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FMC); - // declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(DCMI); - declare!(FPU); - declare!(UART7); - declare!(UART8); - declare!(SPI4); - declare!(LCD_TFT); - declare!(LCD_TFT_1); -} - -#[cfg(feature = "stm32f469")] -mod irqs { - use super::*; - - declare!(WWDG); - declare!(PVD); - declare!(TAMP_STAMP); - declare!(RTC_WKUP); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0); - declare!(EXTI1); - declare!(EXTI2); - declare!(EXTI3); - declare!(EXTI4); - declare!(DMA1_STREAM0); - declare!(DMA1_STREAM1); - declare!(DMA1_STREAM2); - declare!(DMA1_STREAM3); - declare!(DMA1_STREAM4); - declare!(DMA1_STREAM5); - declare!(DMA1_STREAM6); - declare!(ADC); - declare!(CAN1_TX); - declare!(CAN1_RX0); - declare!(CAN1_RX1); - declare!(CAN1_SCE); - declare!(EXTI9_5); - declare!(TIM1_BRK_TIM9); - declare!(TIM1_UP_TIM10); - declare!(TIM1_TRG_COM_TIM11); - declare!(TIM1_CC); - declare!(TIM2); - declare!(TIM3); - declare!(TIM4); - declare!(I2C1_EV); - declare!(I2C1_ER); - declare!(I2C2_EV); - declare!(I2C2_ER); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(USART3); - declare!(EXTI15_10); - declare!(RTC_ALARM); - declare!(OTG_FS_WKUP); - declare!(TIM8_BRK_TIM12); - declare!(TIM8_UP_TIM13); - declare!(TIM8_TRG_COM_TIM14); - declare!(TIM8_CC); - declare!(DMA1_STREAM7); - declare!(FMC); - declare!(SDIO); - declare!(TIM5); - declare!(SPI3); - declare!(UART4); - declare!(UART5); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(DMA2_STREAM0); - declare!(DMA2_STREAM1); - declare!(DMA2_STREAM2); - declare!(DMA2_STREAM3); - declare!(DMA2_STREAM4); - declare!(ETH); - declare!(ETH_WKUP); - declare!(CAN2_TX); - declare!(CAN2_RX0); - declare!(CAN2_RX1); - declare!(CAN2_SCE); - declare!(OTG_FS); - declare!(DMA2_STREAM5); - declare!(DMA2_STREAM6); - declare!(DMA2_STREAM7); - declare!(USART6); - declare!(I2C3_EV); - declare!(I2C3_ER); - declare!(OTG_HS_EP1_OUT); - declare!(OTG_HS_EP1_IN); - declare!(OTG_HS_WKUP); - declare!(OTG_HS); - declare!(DCMI); - declare!(CRYP); - declare!(HASH_RNG); - declare!(FPU); - declare!(UART7); - declare!(UART8); - declare!(SPI4); - declare!(SPI5); - declare!(SPI6); - declare!(SAI1); - declare!(LCD_TFT); - declare!(LCD_TFT_1); - declare!(DMA2D); - declare!(QUADSPI); - declare!(DSIHOST); -} - -#[cfg(feature = "stm32l0x1")] -mod irqs { - use super::*; - declare!(WWDG); - declare!(PVD); - declare!(RTC); - declare!(FLASH); - declare!(RCC); - declare!(EXTI0_1); - declare!(EXTI2_3); - declare!(EXTI4_15); - declare!(DMA1_CHANNEL1); - declare!(DMA1_CHANNEL2_3); - declare!(DMA1_CHANNEL4_7); - declare!(ADC_COMP); - declare!(LPTIM1); - declare!(USART4_USART5); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6); - declare!(TIM7); - declare!(TIM21); - declare!(I2C3); - declare!(TIM22); - declare!(I2C1); - declare!(I2C2); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(AES_RNG_LPUART1); -} - -#[cfg(feature = "stm32l0x2")] -mod irqs { - use super::*; - declare!(WWDG); - declare!(PVD); - declare!(RTC); - declare!(RCC); - declare!(EXTI0_1); - declare!(EXTI2_3); - declare!(EXTI4_15); - declare!(TSC); - declare!(DMA1_CHANNEL1); - declare!(DMA1_CHANNEL2_3); - declare!(DMA1_CHANNEL4_7); - declare!(ADC_COMP); - declare!(LPTIM1); - declare!(USART4_USART5); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM21); - declare!(I2C3); - declare!(TIM22); - declare!(I2C1); - declare!(I2C2); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(AES_RNG_LPUART1); - declare!(USB); -} - -#[cfg(feature = "stm32l0x3")] -mod irqs { - use super::*; - declare!(WWDG); - declare!(PVD); - declare!(RTC); - declare!(RCC); - declare!(EXTI0_1); - declare!(EXTI2_3); - declare!(EXTI4_15); - declare!(TSC); - declare!(DMA1_CHANNEL1); - declare!(DMA1_CHANNEL2_3); - declare!(DMA1_CHANNEL4_7); - declare!(ADC_COMP); - declare!(LPTIM1); - declare!(USART4_USART5); - declare!(TIM2); - declare!(TIM3); - declare!(TIM6_DAC); - declare!(TIM7); - declare!(TIM21); - declare!(I2C3); - declare!(TIM22); - declare!(I2C1); - declare!(I2C2); - declare!(SPI1); - declare!(SPI2); - declare!(USART1); - declare!(USART2); - declare!(AES_RNG_LPUART1); - declare!(LCD); - declare!(USB); -} - -pub use irqs::*; diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 6d34a616..4ea5f952 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -9,6 +9,7 @@ // This must go FIRST so that all the other modules see its macros. pub mod fmt; +use embassy::interrupt::{Interrupt, InterruptExt}; pub(crate) use stm32_metapac as pac; #[macro_use] @@ -16,7 +17,6 @@ pub mod exti; #[macro_use] pub mod gpio; //pub mod rtc; -//pub mod interrupt; #[macro_use] pub mod usart; @@ -25,4 +25,33 @@ pub mod rng; // This must go LAST so that it sees the `impl_foo!` macros mod chip; -pub use chip::{peripherals, Peripherals}; +pub use chip::{interrupt, peripherals, Peripherals}; +pub use embassy_macros::interrupt; + +#[non_exhaustive] +pub struct Config { + _private: (), +} + +impl Default for Config { + fn default() -> Self { + Self { _private: () } + } +} + +/// Initialize embassy. +pub fn init(_config: Config) -> Peripherals { + let p = Peripherals::take(); + + unsafe { + interrupt::EXTI0::steal().enable(); + interrupt::EXTI1::steal().enable(); + interrupt::EXTI2::steal().enable(); + interrupt::EXTI3::steal().enable(); + interrupt::EXTI4::steal().enable(); + interrupt::EXTI9_5::steal().enable(); + interrupt::EXTI15_10::steal().enable(); + } + + p +}