Flush MISO before transfer operation

embassy-lora/src/sx127x/sx127x_lora/mod.rs

@@ -560,9 +560,8 @@ where
         byte: u8,
     ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
         self.cs.set_low().map_err(CS)?;
-        let mut rx = [0, 0];
         let buffer = [reg | 0x80, byte];
-        self.spi.read_write(&mut rx, &buffer).await.map_err(SPI)?;
+        self.spi.write(&buffer).await.map_err(SPI)?;
         self.cs.set_high().map_err(CS)?;
         Ok(())
     }

embassy-stm32/src/spi/v2.rs

@@ -262,6 +262,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr2().modify(|reg| {
                 reg.set_rxdmaen(true);
             });
+
+            // Flush the read buffer to avoid errornous data from being read
+            while T::regs().sr().read().rxne() {
+                let _ = T::regs().dr().read();
+            }
         }
         Self::set_word_size(WordSize::EightBit);
 

embassy-stm32/src/spi/v3.rs

@@ -284,6 +284,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cfg1().modify(|reg| {
                 reg.set_rxdmaen(true);
             });
+
+            // Flush the read buffer to avoid errornous data from being read
+            while T::regs().sr().read().rxp() {
+                let _ = T::regs().rxdr().read();
+            }
         }
 
         let rx_request = self.rxdma.request();