rp: update rp-pac.
This commit is contained in:
Dario Nieuwenhuis
@ -144,7 +144,7 @@ pub(crate) unsafe fn init() {
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#[cfg(feature = "rt")]
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#[interrupt]
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unsafe fn IO_IRQ_BANK0() {
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fn IO_IRQ_BANK0() {
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let cpu = SIO.cpuid().read() as usize;
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// There are two sets of interrupt registers, one for cpu0 and one for cpu1
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// and here we are selecting the set that belongs to the currently executing
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@ -185,46 +185,44 @@ struct InputFuture<'a, T: Pin> {
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impl<'d, T: Pin> InputFuture<'d, T> {
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pub fn new(pin: impl Peripheral<P = T> + 'd, level: InterruptTrigger) -> Self {
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into_ref!(pin);
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unsafe {
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let pin_group = (pin.pin() % 8) as usize;
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// first, clear the INTR register bits. without this INTR will still
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// contain reports of previous edges, causing the IRQ to fire early
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// on stale state. clearing these means that we can only detect edges
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// that occur *after* the clear happened, but since both this and the
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// alternative are fundamentally racy it's probably fine.
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// (the alternative being checking the current level and waiting for
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// its inverse, but that requires reading the current level and thus
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// missing anything that happened before the level was read.)
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pac::IO_BANK0.intr(pin.pin() as usize / 8).write(|w| {
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w.set_edge_high(pin_group, true);
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w.set_edge_low(pin_group, true);
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});
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let pin_group = (pin.pin() % 8) as usize;
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// first, clear the INTR register bits. without this INTR will still
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// contain reports of previous edges, causing the IRQ to fire early
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// on stale state. clearing these means that we can only detect edges
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// that occur *after* the clear happened, but since both this and the
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// alternative are fundamentally racy it's probably fine.
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// (the alternative being checking the current level and waiting for
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// its inverse, but that requires reading the current level and thus
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// missing anything that happened before the level was read.)
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pac::IO_BANK0.intr(pin.pin() as usize / 8).write(|w| {
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w.set_edge_high(pin_group, true);
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w.set_edge_low(pin_group, true);
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});
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// Each INTR register is divided into 8 groups, one group for each
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// pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW,
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// and EGDE_HIGH.
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pin.int_proc()
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.inte((pin.pin() / 8) as usize)
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.write_set(|w| match level {
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InterruptTrigger::LevelHigh => {
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trace!("InputFuture::new enable LevelHigh for pin {}", pin.pin());
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w.set_level_high(pin_group, true);
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}
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InterruptTrigger::LevelLow => {
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w.set_level_low(pin_group, true);
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}
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InterruptTrigger::EdgeHigh => {
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w.set_edge_high(pin_group, true);
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}
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InterruptTrigger::EdgeLow => {
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w.set_edge_low(pin_group, true);
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}
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InterruptTrigger::AnyEdge => {
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w.set_edge_high(pin_group, true);
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w.set_edge_low(pin_group, true);
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}
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});
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}
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// Each INTR register is divided into 8 groups, one group for each
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// pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW,
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// and EGDE_HIGH.
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pin.int_proc()
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.inte((pin.pin() / 8) as usize)
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.write_set(|w| match level {
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InterruptTrigger::LevelHigh => {
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trace!("InputFuture::new enable LevelHigh for pin {}", pin.pin());
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w.set_level_high(pin_group, true);
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}
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InterruptTrigger::LevelLow => {
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w.set_level_low(pin_group, true);
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}
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InterruptTrigger::EdgeHigh => {
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w.set_edge_high(pin_group, true);
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}
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InterruptTrigger::EdgeLow => {
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w.set_edge_low(pin_group, true);
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}
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InterruptTrigger::AnyEdge => {
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w.set_edge_high(pin_group, true);
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w.set_edge_low(pin_group, true);
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}
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});
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Self { pin, level }
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}
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@ -242,7 +240,7 @@ impl<'d, T: Pin> Future for InputFuture<'d, T> {
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// then we want to access the interrupt enable register for our
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// pin (there are 4 of these PROC0_INTE0, PROC0_INTE1, PROC0_INTE2, and
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// PROC0_INTE3 per cpu).
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let inte: pac::io::regs::Int = unsafe { self.pin.int_proc().inte((self.pin.pin() / 8) as usize).read() };
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let inte: pac::io::regs::Int = self.pin.int_proc().inte((self.pin.pin() / 8) as usize).read();
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// The register is divided into groups of four, one group for
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// each pin. Each group consists of four trigger levels LEVEL_LOW,
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// LEVEL_HIGH, EDGE_LOW, and EDGE_HIGH for each pin.
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@ -449,15 +447,13 @@ impl<'d, T: Pin> Flex<'d, T> {
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pub fn new(pin: impl Peripheral<P = T> + 'd) -> Self {
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into_ref!(pin);
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unsafe {
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pin.pad_ctrl().write(|w| {
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w.set_ie(true);
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});
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pin.pad_ctrl().write(|w| {
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w.set_ie(true);
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});
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pin.io().ctrl().write(|w| {
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w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0.0);
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});
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}
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pin.io().ctrl().write(|w| {
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w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0.0);
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});
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Self { pin }
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}
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@ -470,43 +466,37 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// Set the pin's pull.
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#[inline]
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pub fn set_pull(&mut self, pull: Pull) {
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unsafe {
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self.pin.pad_ctrl().modify(|w| {
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w.set_ie(true);
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let (pu, pd) = match pull {
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Pull::Up => (true, false),
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Pull::Down => (false, true),
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Pull::None => (false, false),
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};
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w.set_pue(pu);
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w.set_pde(pd);
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});
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}
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self.pin.pad_ctrl().modify(|w| {
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w.set_ie(true);
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let (pu, pd) = match pull {
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Pull::Up => (true, false),
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Pull::Down => (false, true),
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Pull::None => (false, false),
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};
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w.set_pue(pu);
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w.set_pde(pd);
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});
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}
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/// Set the pin's drive strength.
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#[inline]
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pub fn set_drive_strength(&mut self, strength: Drive) {
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unsafe {
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self.pin.pad_ctrl().modify(|w| {
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w.set_drive(match strength {
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Drive::_2mA => pac::pads::vals::Drive::_2MA,
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Drive::_4mA => pac::pads::vals::Drive::_4MA,
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Drive::_8mA => pac::pads::vals::Drive::_8MA,
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Drive::_12mA => pac::pads::vals::Drive::_12MA,
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});
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self.pin.pad_ctrl().modify(|w| {
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w.set_drive(match strength {
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Drive::_2mA => pac::pads::vals::Drive::_2MA,
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Drive::_4mA => pac::pads::vals::Drive::_4MA,
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Drive::_8mA => pac::pads::vals::Drive::_8MA,
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Drive::_12mA => pac::pads::vals::Drive::_12MA,
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});
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}
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});
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}
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// Set the pin's slew rate.
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#[inline]
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pub fn set_slew_rate(&mut self, slew_rate: SlewRate) {
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unsafe {
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self.pin.pad_ctrl().modify(|w| {
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w.set_slewfast(slew_rate == SlewRate::Fast);
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});
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}
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self.pin.pad_ctrl().modify(|w| {
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w.set_slewfast(slew_rate == SlewRate::Fast);
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});
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}
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/// Put the pin into input mode.
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@ -514,7 +504,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// The pull setting is left unchanged.
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#[inline]
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pub fn set_as_input(&mut self) {
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unsafe { self.pin.sio_oe().value_clr().write_value(self.bit()) }
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self.pin.sio_oe().value_clr().write_value(self.bit())
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}
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/// Put the pin into output mode.
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@ -523,17 +513,17 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// at a specific level, call `set_high`/`set_low` on the pin first.
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#[inline]
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pub fn set_as_output(&mut self) {
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unsafe { self.pin.sio_oe().value_set().write_value(self.bit()) }
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self.pin.sio_oe().value_set().write_value(self.bit())
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}
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#[inline]
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fn is_set_as_output(&self) -> bool {
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unsafe { (self.pin.sio_oe().value().read() & self.bit()) != 0 }
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(self.pin.sio_oe().value().read() & self.bit()) != 0
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}
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#[inline]
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pub fn toggle_set_as_output(&mut self) {
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unsafe { self.pin.sio_oe().value_xor().write_value(self.bit()) }
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self.pin.sio_oe().value_xor().write_value(self.bit())
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}
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#[inline]
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@ -543,7 +533,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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#[inline]
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pub fn is_low(&self) -> bool {
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unsafe { self.pin.sio_in().read() & self.bit() == 0 }
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self.pin.sio_in().read() & self.bit() == 0
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}
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/// Returns current pin level
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@ -555,13 +545,13 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// Set the output as high.
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#[inline]
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pub fn set_high(&mut self) {
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unsafe { self.pin.sio_out().value_set().write_value(self.bit()) }
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self.pin.sio_out().value_set().write_value(self.bit())
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}
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/// Set the output as low.
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#[inline]
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pub fn set_low(&mut self) {
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unsafe { self.pin.sio_out().value_clr().write_value(self.bit()) }
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self.pin.sio_out().value_clr().write_value(self.bit())
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}
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/// Set the output level.
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@ -576,7 +566,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// Is the output level high?
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#[inline]
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pub fn is_set_high(&self) -> bool {
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unsafe { (self.pin.sio_out().value().read() & self.bit()) == 0 }
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(self.pin.sio_out().value().read() & self.bit()) == 0
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}
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/// Is the output level low?
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@ -594,7 +584,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// Toggle pin output
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#[inline]
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pub fn toggle(&mut self) {
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unsafe { self.pin.sio_out().value_xor().write_value(self.bit()) }
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self.pin.sio_out().value_xor().write_value(self.bit())
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}
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#[inline]
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@ -626,12 +616,10 @@ impl<'d, T: Pin> Flex<'d, T> {
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impl<'d, T: Pin> Drop for Flex<'d, T> {
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#[inline]
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fn drop(&mut self) {
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unsafe {
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self.pin.pad_ctrl().write(|_| {});
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self.pin.io().ctrl().write(|w| {
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w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL.0);
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});
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}
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self.pin.pad_ctrl().write(|_| {});
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self.pin.io().ctrl().write(|w| {
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w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL.0);
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});
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}
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}
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@ -688,7 +676,7 @@ pub(crate) mod sealed {
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Bank::Bank0 => crate::pac::IO_BANK0,
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Bank::Qspi => crate::pac::IO_QSPI,
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};
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let proc = unsafe { SIO.cpuid().read() };
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let proc = SIO.cpuid().read();
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io_block.int_proc(proc as _)
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}
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}
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