rp: update rp-pac.
This commit is contained in:
Dario Nieuwenhuis
@ -79,39 +79,37 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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) -> Self {
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into_ref!(inner);
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unsafe {
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let p = inner.regs();
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let (presc, postdiv) = calc_prescs(config.frequency);
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let p = inner.regs();
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let (presc, postdiv) = calc_prescs(config.frequency);
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().write(|w| {
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w.set_dss(0b0111); // 8bit
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w.set_spo(config.polarity == Polarity::IdleHigh);
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w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
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w.set_scr(postdiv);
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});
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().write(|w| {
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w.set_dss(0b0111); // 8bit
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w.set_spo(config.polarity == Polarity::IdleHigh);
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w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
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w.set_scr(postdiv);
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});
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// Always enable DREQ signals -- harmless if DMA is not listening
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p.dmacr().write(|reg| {
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reg.set_rxdmae(true);
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reg.set_txdmae(true);
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});
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// Always enable DREQ signals -- harmless if DMA is not listening
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p.dmacr().write(|reg| {
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reg.set_rxdmae(true);
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reg.set_txdmae(true);
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});
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// finally, enable.
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p.cr1().write(|w| w.set_sse(true));
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// finally, enable.
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p.cr1().write(|w| w.set_sse(true));
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if let Some(pin) = &clk {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &mosi {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &miso {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &cs {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &clk {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &mosi {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &miso {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &cs {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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Self {
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inner,
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@ -122,60 +120,52 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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}
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pub fn blocking_write(&mut self, data: &[u8]) -> Result<(), Error> {
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unsafe {
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let p = self.inner.regs();
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for &b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(b as _));
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while !p.sr().read().rne() {}
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let _ = p.dr().read();
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}
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let p = self.inner.regs();
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for &b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(b as _));
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while !p.sr().read().rne() {}
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let _ = p.dr().read();
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}
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self.flush()?;
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Ok(())
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}
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pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
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unsafe {
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let p = self.inner.regs();
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for b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(*b as _));
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while !p.sr().read().rne() {}
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*b = p.dr().read().data() as u8;
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}
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let p = self.inner.regs();
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for b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(*b as _));
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while !p.sr().read().rne() {}
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*b = p.dr().read().data() as u8;
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}
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self.flush()?;
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Ok(())
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}
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pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
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unsafe {
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let p = self.inner.regs();
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for b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(0));
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while !p.sr().read().rne() {}
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*b = p.dr().read().data() as u8;
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}
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let p = self.inner.regs();
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for b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(0));
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while !p.sr().read().rne() {}
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*b = p.dr().read().data() as u8;
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}
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self.flush()?;
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Ok(())
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}
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pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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unsafe {
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let p = self.inner.regs();
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let len = read.len().max(write.len());
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for i in 0..len {
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let wb = write.get(i).copied().unwrap_or(0);
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(wb as _));
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while !p.sr().read().rne() {}
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let rb = p.dr().read().data() as u8;
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if let Some(r) = read.get_mut(i) {
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*r = rb;
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}
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let p = self.inner.regs();
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let len = read.len().max(write.len());
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for i in 0..len {
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let wb = write.get(i).copied().unwrap_or(0);
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(wb as _));
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while !p.sr().read().rne() {}
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let rb = p.dr().read().data() as u8;
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if let Some(r) = read.get_mut(i) {
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*r = rb;
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}
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}
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self.flush()?;
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@ -183,29 +173,25 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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}
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pub fn flush(&mut self) -> Result<(), Error> {
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unsafe {
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let p = self.inner.regs();
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while p.sr().read().bsy() {}
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}
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let p = self.inner.regs();
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while p.sr().read().bsy() {}
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Ok(())
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}
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pub fn set_frequency(&mut self, freq: u32) {
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let (presc, postdiv) = calc_prescs(freq);
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let p = self.inner.regs();
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unsafe {
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// disable
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p.cr1().write(|w| w.set_sse(false));
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// disable
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p.cr1().write(|w| w.set_sse(false));
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// change stuff
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().modify(|w| {
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w.set_scr(postdiv);
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});
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// change stuff
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().modify(|w| {
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w.set_scr(postdiv);
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});
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// enable
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p.cr1().write(|w| w.set_sse(true));
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}
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// enable
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p.cr1().write(|w| w.set_sse(true));
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}
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}
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@ -337,21 +323,19 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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let tx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(tx_ch, buffer, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
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crate::dma::write(tx_ch, buffer, self.inner.regs().dr().as_ptr() as *mut _, T::TX_DREQ)
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};
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tx_transfer.await;
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let p = self.inner.regs();
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unsafe {
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while p.sr().read().bsy() {}
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while p.sr().read().bsy() {}
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// clear RX FIFO contents to prevent stale reads
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while p.sr().read().rne() {
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let _: u16 = p.dr().read().data();
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}
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// clear RX overrun interrupt
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p.icr().write(|w| w.set_roric(true));
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// clear RX FIFO contents to prevent stale reads
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while p.sr().read().rne() {
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let _: u16 = p.dr().read().data();
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}
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// clear RX overrun interrupt
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p.icr().write(|w| w.set_roric(true));
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Ok(())
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}
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@ -363,14 +347,19 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, buffer, T::RX_DREQ)
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crate::dma::read(rx_ch, self.inner.regs().dr().as_ptr() as *const _, buffer, T::RX_DREQ)
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};
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write_repeated(tx_ch, self.inner.regs().dr().ptr() as *mut u8, buffer.len(), T::TX_DREQ)
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crate::dma::write_repeated(
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tx_ch,
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self.inner.regs().dr().as_ptr() as *mut u8,
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buffer.len(),
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T::TX_DREQ,
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)
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};
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join(tx_transfer, rx_transfer).await;
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Ok(())
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@ -394,7 +383,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, rx_ptr, T::RX_DREQ)
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crate::dma::read(rx_ch, self.inner.regs().dr().as_ptr() as *const _, rx_ptr, T::RX_DREQ)
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};
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let mut tx_ch = self.tx_dma.as_mut().unwrap();
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@ -403,13 +392,13 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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let tx_transfer = async {
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let p = self.inner.regs();
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unsafe {
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crate::dma::write(&mut tx_ch, tx_ptr, p.dr().ptr() as *mut _, T::TX_DREQ).await;
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crate::dma::write(&mut tx_ch, tx_ptr, p.dr().as_ptr() as *mut _, T::TX_DREQ).await;
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if rx_len > tx_len {
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let write_bytes_len = rx_len - tx_len;
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// write dummy data
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// this will disable incrementation of the buffers
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crate::dma::write_repeated(tx_ch, p.dr().ptr() as *mut u8, write_bytes_len, T::TX_DREQ).await
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crate::dma::write_repeated(tx_ch, p.dr().as_ptr() as *mut u8, write_bytes_len, T::TX_DREQ).await
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}
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}
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};
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@ -418,16 +407,14 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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// if tx > rx we should clear any overflow of the FIFO SPI buffer
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if tx_len > rx_len {
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let p = self.inner.regs();
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unsafe {
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while p.sr().read().bsy() {}
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while p.sr().read().bsy() {}
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// clear RX FIFO contents to prevent stale reads
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while p.sr().read().rne() {
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let _: u16 = p.dr().read().data();
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}
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// clear RX overrun interrupt
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p.icr().write(|w| w.set_roric(true));
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// clear RX FIFO contents to prevent stale reads
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while p.sr().read().rne() {
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let _: u16 = p.dr().read().data();
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}
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// clear RX overrun interrupt
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p.icr().write(|w| w.set_roric(true));
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}
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Ok(())
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@ -625,14 +612,12 @@ impl<'d, T: Instance, M: Mode> SetConfig for Spi<'d, T, M> {
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fn set_config(&mut self, config: &Self::Config) {
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let p = self.inner.regs();
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let (presc, postdiv) = calc_prescs(config.frequency);
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unsafe {
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().write(|w| {
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w.set_dss(0b0111); // 8bit
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w.set_spo(config.polarity == Polarity::IdleHigh);
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w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
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w.set_scr(postdiv);
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});
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}
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().write(|w| {
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w.set_dss(0b0111); // 8bit
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w.set_spo(config.polarity == Polarity::IdleHigh);
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w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
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w.set_scr(postdiv);
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});
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}
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}
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