rp: update rp-pac.
This commit is contained in:
Dario Nieuwenhuis
@ -73,16 +73,14 @@ pub(crate) fn init_buffers<'d, T: Instance + 'd>(
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// we clear it after it happens. The downside is that the we manually have
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// to pend the ISR when we want data transmission to start.
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let regs = T::regs();
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unsafe {
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regs.uartimsc().write(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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w.set_txim(true);
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});
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regs.uartimsc().write(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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w.set_txim(true);
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});
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T::Interrupt::unpend();
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T::Interrupt::enable();
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};
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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}
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impl<'d, T: Instance> BufferedUart<'d, T> {
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@ -247,12 +245,10 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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// (Re-)Enable the interrupt to receive more data in case it was
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// disabled because the buffer was full or errors were detected.
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let regs = T::regs();
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unsafe {
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regs.uartimsc().write_set(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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regs.uartimsc().write_set(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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Poll::Ready(result)
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}
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@ -299,12 +295,10 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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// (Re-)Enable the interrupt to receive more data in case it was
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// disabled because the buffer was full or errors were detected.
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let regs = T::regs();
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unsafe {
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regs.uartimsc().write_set(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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regs.uartimsc().write_set(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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}
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@ -414,7 +408,7 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
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}
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pub fn busy(&self) -> bool {
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unsafe { T::regs().uartfr().read().busy() }
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T::regs().uartfr().read().busy()
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}
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/// Assert a break condition after waiting for the transmit buffers to empty,
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@ -426,42 +420,35 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
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/// for the transmit fifo to empty, which may take a while on slow links.
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pub async fn send_break(&mut self, bits: u32) {
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let regs = T::regs();
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let bits = bits.max(unsafe {
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let bits = bits.max({
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let lcr = regs.uartlcr_h().read();
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let width = lcr.wlen() as u32 + 5;
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let parity = lcr.pen() as u32;
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let stops = 1 + lcr.stp2() as u32;
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2 * (1 + width + parity + stops)
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});
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let divx64 = unsafe {
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((regs.uartibrd().read().baud_divint() as u32) << 6) + regs.uartfbrd().read().baud_divfrac() as u32
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} as u64;
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let divx64 = (((regs.uartibrd().read().baud_divint() as u32) << 6)
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+ regs.uartfbrd().read().baud_divfrac() as u32) as u64;
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let div_clk = clk_peri_freq() as u64 * 64;
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let wait_usecs = (1_000_000 * bits as u64 * divx64 * 16 + div_clk - 1) / div_clk;
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Self::flush().await.unwrap();
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while self.busy() {}
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unsafe {
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regs.uartlcr_h().write_set(|w| w.set_brk(true));
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}
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regs.uartlcr_h().write_set(|w| w.set_brk(true));
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Timer::after(Duration::from_micros(wait_usecs)).await;
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unsafe {
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regs.uartlcr_h().write_clear(|w| w.set_brk(true));
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}
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regs.uartlcr_h().write_clear(|w| w.set_brk(true));
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}
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}
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impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
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fn drop(&mut self) {
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let state = T::buffered_state();
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unsafe {
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state.rx_buf.deinit();
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unsafe { state.rx_buf.deinit() }
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// TX is inactive if the the buffer is not available.
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// We can now unregister the interrupt handler
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if state.tx_buf.len() == 0 {
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T::Interrupt::disable();
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}
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// TX is inactive if the the buffer is not available.
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// We can now unregister the interrupt handler
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if state.tx_buf.len() == 0 {
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T::Interrupt::disable();
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}
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}
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}
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@ -469,14 +456,12 @@ impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
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impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
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fn drop(&mut self) {
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let state = T::buffered_state();
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unsafe {
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state.tx_buf.deinit();
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unsafe { state.tx_buf.deinit() }
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// RX is inactive if the the buffer is not available.
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// We can now unregister the interrupt handler
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if state.rx_buf.len() == 0 {
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T::Interrupt::disable();
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}
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// RX is inactive if the the buffer is not available.
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// We can now unregister the interrupt handler
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if state.rx_buf.len() == 0 {
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T::Interrupt::disable();
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}
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}
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}
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@ -494,94 +479,92 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for BufferedInterr
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let s = T::buffered_state();
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unsafe {
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// Clear TX and error interrupt flags
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// RX interrupt flags are cleared by reading from the FIFO.
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let ris = r.uartris().read();
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r.uarticr().write(|w| {
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w.set_txic(ris.txris());
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w.set_feic(ris.feris());
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w.set_peic(ris.peris());
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w.set_beic(ris.beris());
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w.set_oeic(ris.oeris());
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});
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// Clear TX and error interrupt flags
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// RX interrupt flags are cleared by reading from the FIFO.
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let ris = r.uartris().read();
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r.uarticr().write(|w| {
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w.set_txic(ris.txris());
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w.set_feic(ris.feris());
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w.set_peic(ris.peris());
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w.set_beic(ris.beris());
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w.set_oeic(ris.oeris());
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});
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trace!("on_interrupt ris={:#X}", ris.0);
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trace!("on_interrupt ris={:#X}", ris.0);
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// Errors
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if ris.feris() {
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warn!("Framing error");
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}
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if ris.peris() {
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warn!("Parity error");
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}
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if ris.beris() {
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warn!("Break error");
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}
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if ris.oeris() {
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warn!("Overrun error");
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}
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// RX
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let mut rx_writer = s.rx_buf.writer();
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let rx_buf = rx_writer.push_slice();
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let mut n_read = 0;
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let mut error = false;
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for rx_byte in rx_buf {
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if r.uartfr().read().rxfe() {
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break;
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}
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let dr = r.uartdr().read();
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if (dr.0 >> 8) != 0 {
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s.rx_error.fetch_or((dr.0 >> 8) as u8, Ordering::Relaxed);
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error = true;
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// only fill the buffer with valid characters. the current character is fine
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// if the error is an overrun, but if we add it to the buffer we'll report
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// the overrun one character too late. drop it instead and pretend we were
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// a bit slower at draining the rx fifo than we actually were.
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// this is consistent with blocking uart error reporting.
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break;
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}
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*rx_byte = dr.data();
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n_read += 1;
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}
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if n_read > 0 {
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rx_writer.push_done(n_read);
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s.rx_waker.wake();
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} else if error {
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s.rx_waker.wake();
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}
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// Disable any further RX interrupts when the buffer becomes full or
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// errors have occurred. This lets us buffer additional errors in the
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// fifo without needing more error storage locations, and most applications
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// will want to do a full reset of their uart state anyway once an error
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// has happened.
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if s.rx_buf.is_full() || error {
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r.uartimsc().write_clear(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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// TX
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let mut tx_reader = s.tx_buf.reader();
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let tx_buf = tx_reader.pop_slice();
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let mut n_written = 0;
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for tx_byte in tx_buf.iter_mut() {
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if r.uartfr().read().txff() {
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break;
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}
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r.uartdr().write(|w| w.set_data(*tx_byte));
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n_written += 1;
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}
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if n_written > 0 {
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tx_reader.pop_done(n_written);
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s.tx_waker.wake();
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}
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// The TX interrupt only triggers once when the FIFO threshold is
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// crossed. No need to disable it when the buffer becomes empty
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// as it does re-trigger anymore once we have cleared it.
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// Errors
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if ris.feris() {
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warn!("Framing error");
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}
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if ris.peris() {
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warn!("Parity error");
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}
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if ris.beris() {
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warn!("Break error");
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}
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if ris.oeris() {
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warn!("Overrun error");
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}
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// RX
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let mut rx_writer = unsafe { s.rx_buf.writer() };
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let rx_buf = rx_writer.push_slice();
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let mut n_read = 0;
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let mut error = false;
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for rx_byte in rx_buf {
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if r.uartfr().read().rxfe() {
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break;
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}
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let dr = r.uartdr().read();
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if (dr.0 >> 8) != 0 {
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s.rx_error.fetch_or((dr.0 >> 8) as u8, Ordering::Relaxed);
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error = true;
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// only fill the buffer with valid characters. the current character is fine
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// if the error is an overrun, but if we add it to the buffer we'll report
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// the overrun one character too late. drop it instead and pretend we were
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// a bit slower at draining the rx fifo than we actually were.
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// this is consistent with blocking uart error reporting.
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break;
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}
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*rx_byte = dr.data();
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n_read += 1;
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}
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if n_read > 0 {
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rx_writer.push_done(n_read);
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s.rx_waker.wake();
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} else if error {
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s.rx_waker.wake();
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}
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// Disable any further RX interrupts when the buffer becomes full or
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// errors have occurred. This lets us buffer additional errors in the
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// fifo without needing more error storage locations, and most applications
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// will want to do a full reset of their uart state anyway once an error
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// has happened.
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if s.rx_buf.is_full() || error {
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r.uartimsc().write_clear(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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// TX
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let mut tx_reader = unsafe { s.tx_buf.reader() };
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let tx_buf = tx_reader.pop_slice();
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let mut n_written = 0;
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for tx_byte in tx_buf.iter_mut() {
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if r.uartfr().read().txff() {
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break;
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}
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r.uartdr().write(|w| w.set_data(*tx_byte));
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n_written += 1;
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}
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if n_written > 0 {
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tx_reader.pop_done(n_written);
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s.tx_waker.wake();
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}
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// The TX interrupt only triggers once when the FIFO threshold is
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// crossed. No need to disable it when the buffer becomes empty
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// as it does re-trigger anymore once we have cleared it.
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}
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}
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@ -695,24 +678,22 @@ mod eh02 {
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fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
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let r = T::regs();
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unsafe {
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if r.uartfr().read().rxfe() {
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return Err(nb::Error::WouldBlock);
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}
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if r.uartfr().read().rxfe() {
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return Err(nb::Error::WouldBlock);
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}
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let dr = r.uartdr().read();
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let dr = r.uartdr().read();
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if dr.oe() {
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Err(nb::Error::Other(Error::Overrun))
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} else if dr.be() {
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Err(nb::Error::Other(Error::Break))
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} else if dr.pe() {
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Err(nb::Error::Other(Error::Parity))
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} else if dr.fe() {
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Err(nb::Error::Other(Error::Framing))
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} else {
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Ok(dr.data())
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}
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if dr.oe() {
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Err(nb::Error::Other(Error::Overrun))
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} else if dr.be() {
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Err(nb::Error::Other(Error::Break))
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} else if dr.pe() {
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Err(nb::Error::Other(Error::Parity))
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} else if dr.fe() {
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Err(nb::Error::Other(Error::Framing))
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} else {
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Ok(dr.data())
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}
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}
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}
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