lint

cyw43/src/bluetooth.rs

@@ -1,7 +1,9 @@
-use embassy_time::{Timer, Duration};
+use embassy_time::{Duration, Timer};
 use embedded_hal_1::digital::OutputPin;
 
-use crate::{consts::*, CHIP, bus::Bus, SpiBusCyw43};
+use crate::bus::Bus;
+use crate::consts::*;
+use crate::{SpiBusCyw43, CHIP};
 
 #[derive(Debug)]
 pub(crate) struct CybtFwCb<'a> {
@@ -56,8 +58,10 @@ pub(crate) fn cybt_fw_get_data(p_btfw_cb: &mut CybtFwCb, hfd: &mut HexFileData)
                 hfd.addr_mode = BTFW_ADDR_MODE_SEGMENT;
             }
             BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS => {
-                abs_base_addr32 = (hfd.p_ds[0] as u32) << 24 | (hfd.p_ds[1] as u32) << 16 |
+                abs_base_addr32 = (hfd.p_ds[0] as u32) << 24
-                                  (hfd.p_ds[2] as u32) << 8 | hfd.p_ds[3] as u32;
+                    | (hfd.p_ds[1] as u32) << 16
+                    | (hfd.p_ds[2] as u32) << 8
+                    | hfd.p_ds[3] as u32;
                 hfd.addr_mode = BTFW_ADDR_MODE_LINEAR32;
             }
             BTFW_HEX_LINE_TYPE_DATA => {
@@ -76,7 +80,10 @@ pub(crate) fn cybt_fw_get_data(p_btfw_cb: &mut CybtFwCb, hfd: &mut HexFileData)
     0
 }
 
-pub(crate) async fn upload_bluetooth_firmware<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>, firmware: &[u8]) {
+pub(crate) async fn upload_bluetooth_firmware<PWR: OutputPin, SPI: SpiBusCyw43>(
+    bus: &mut Bus<PWR, SPI>,
+    firmware: &[u8],
+) {
     // read version
     let version_length = firmware[0];
     let _version = &firmware[1..=version_length as usize];
@@ -220,7 +227,8 @@ pub(crate) async fn bt_set_intr<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<
 }
 
 pub(crate) async fn init_bluetooth<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>, firmware: &[u8]) {
-    bus.bp_write32(CHIP.bluetooth_base_address + BT2WLAN_PWRUP_ADDR, BT2WLAN_PWRUP_WAKE).await;
+    bus.bp_write32(CHIP.bluetooth_base_address + BT2WLAN_PWRUP_ADDR, BT2WLAN_PWRUP_WAKE)
+        .await;
     upload_bluetooth_firmware(bus, firmware).await;
     wait_bt_ready(bus).await;
     // TODO: cybt_init_buffer();

cyw43/src/bus.rs

@@ -101,18 +101,33 @@ where
 
         // TODO: setting this causes total failure (watermark read test fails)
         debug!("write SPI_RESP_DELAY_F1 CYW43_BACKPLANE_READ_PAD_LEN_BYTES");
-        self.write8(FUNC_BUS, SPI_RESP_DELAY_F1, WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE).await;
+        self.write8(FUNC_BUS, SPI_RESP_DELAY_F1, WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE)
+            .await;
 
         // TODO: Make sure error interrupt bits are clear?
         // cyw43_write_reg_u8(self, BUS_FUNCTION, SPI_INTERRUPT_REGISTER, DATA_UNAVAILABLE | COMMAND_ERROR | DATA_ERROR | F1_OVERFLOW) != 0)
         debug!("Make sure error interrupt bits are clear");
-        self.write8(FUNC_BUS, REG_BUS_INTERRUPT, (IRQ_DATA_UNAVAILABLE | IRQ_COMMAND_ERROR | IRQ_DATA_ERROR | IRQ_F1_OVERFLOW) as u8)
+        self.write8(
+            FUNC_BUS,
+            REG_BUS_INTERRUPT,
+            (IRQ_DATA_UNAVAILABLE | IRQ_COMMAND_ERROR | IRQ_DATA_ERROR | IRQ_F1_OVERFLOW) as u8,
+        )
         .await;
 
         // Enable a selection of interrupts
         // TODO: why not all of these F2_F3_FIFO_RD_UNDERFLOW | F2_F3_FIFO_WR_OVERFLOW | COMMAND_ERROR | DATA_ERROR | F2_PACKET_AVAILABLE | F1_OVERFLOW | F1_INTR
         debug!("enable a selection of interrupts");
-        self.write16(FUNC_BUS, REG_BUS_INTERRUPT_ENABLE, IRQ_F2_F3_FIFO_RD_UNDERFLOW | IRQ_F2_F3_FIFO_WR_OVERFLOW | IRQ_COMMAND_ERROR | IRQ_DATA_ERROR | IRQ_F2_PACKET_AVAILABLE | IRQ_F1_OVERFLOW | IRQ_F1_INTR)
+        self.write16(
+            FUNC_BUS,
+            REG_BUS_INTERRUPT_ENABLE,
+            IRQ_F2_F3_FIFO_RD_UNDERFLOW
+                | IRQ_F2_F3_FIFO_WR_OVERFLOW
+                | IRQ_COMMAND_ERROR
+                | IRQ_DATA_ERROR
+                | IRQ_F2_PACKET_AVAILABLE
+                | IRQ_F1_OVERFLOW
+                | IRQ_F1_INTR,
+        )
         .await;
     }
 

cyw43/src/lib.rs

@@ -7,8 +7,8 @@
 // This mod MUST go first, so that the others see its macros.
 pub(crate) mod fmt;
 
-mod bus;
 mod bluetooth;
+mod bus;
 mod consts;
 mod countries;
 mod events;
@@ -214,7 +214,7 @@ pub async fn new<'a, PWR, SPI>(
     pwr: PWR,
     spi: SPI,
     firmware: &[u8],
-    bluetooth_firmware: &[u8]
+    bluetooth_firmware: &[u8],
 ) -> (NetDriver<'a>, Control<'a>, Runner<'a, PWR, SPI>)
 where
     PWR: OutputPin,

cyw43/src/runner.rs

@@ -6,13 +6,13 @@ use embedded_hal_1::digital::OutputPin;
 
 use crate::bus::Bus;
 pub use crate::bus::SpiBusCyw43;
-use crate::{consts::*, bluetooth};
+use crate::consts::*;
 use crate::events::{Event, Events, Status};
 use crate::fmt::Bytes;
 use crate::ioctl::{IoctlState, IoctlType, PendingIoctl};
 use crate::nvram::NVRAM;
 use crate::structs::*;
-use crate::{events, slice8_mut, Core, CHIP, MTU};
+use crate::{bluetooth, events, slice8_mut, Core, CHIP, MTU};
 
 #[cfg(feature = "firmware-logs")]
 struct LogState {
@@ -143,11 +143,15 @@ where
 
         // "Set up the interrupt mask and enable interrupts"
         debug!("setup interrupt mask");
-        self.bus.bp_write32(CHIP.sdiod_core_base_address + SDIO_INT_HOST_MASK, I_HMB_SW_MASK).await;
+        self.bus
+            .bp_write32(CHIP.sdiod_core_base_address + SDIO_INT_HOST_MASK, I_HMB_SW_MASK)
+            .await;
 
         // Set up the interrupt mask and enable interrupts
         debug!("bluetooth setup interrupt mask");
-        self.bus.bp_write32(CHIP.sdiod_core_base_address + SDIO_INT_HOST_MASK, I_HMB_FC_CHANGE).await;
+        self.bus
+            .bp_write32(CHIP.sdiod_core_base_address + SDIO_INT_HOST_MASK, I_HMB_FC_CHANGE)
+            .await;
 
         // TODO: turn interrupts on here or in bus.init()?
         /*self.bus
@@ -187,7 +191,9 @@ where
         let _ = self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_PULL_UP).await;
 
         // start HT clock
-        self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x10).await; // SBSDIO_HT_AVAIL_REQ
+        self.bus
+            .write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x10)
+            .await; // SBSDIO_HT_AVAIL_REQ
         debug!("waiting for HT clock...");
         while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & 0x80 == 0 {}
         debug!("clock ok");