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This commit is contained in:
Brandon Ros 2023-08-20 18:11:49 -04:00
parent 8d588f0abd
commit 861f3566e8
5 changed files with 61 additions and 32 deletions
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32
cyw43/src/bluetooth.rs
View File

@ -1,7 +1,9 @@
use embassy_time::{Timer, Duration}; use embassy_time::{Duration, Timer};
use embedded_hal_1::digital::OutputPin; use embedded_hal_1::digital::OutputPin;
use crate::{consts::*, CHIP, bus::Bus, SpiBusCyw43}; use crate::bus::Bus;
use crate::consts::*;
use crate::{SpiBusCyw43, CHIP};
#[derive(Debug)] #[derive(Debug)]
pub(crate) struct CybtFwCb<'a> { pub(crate) struct CybtFwCb<'a> {
@ -56,8 +58,10 @@ pub(crate) fn cybt_fw_get_data(p_btfw_cb: &mut CybtFwCb, hfd: &mut HexFileData)
hfd.addr_mode = BTFW_ADDR_MODE_SEGMENT; hfd.addr_mode = BTFW_ADDR_MODE_SEGMENT;
} }
BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS => { BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS => {
abs_base_addr32 = (hfd.p_ds[0] as u32) << 24 | (hfd.p_ds[1] as u32) << 16 | abs_base_addr32 = (hfd.p_ds[0] as u32) << 24
(hfd.p_ds[2] as u32) << 8 | hfd.p_ds[3] as u32; | (hfd.p_ds[1] as u32) << 16
| (hfd.p_ds[2] as u32) << 8
| hfd.p_ds[3] as u32;
hfd.addr_mode = BTFW_ADDR_MODE_LINEAR32; hfd.addr_mode = BTFW_ADDR_MODE_LINEAR32;
} }
BTFW_HEX_LINE_TYPE_DATA => { BTFW_HEX_LINE_TYPE_DATA => {
@ -76,14 +80,17 @@ pub(crate) fn cybt_fw_get_data(p_btfw_cb: &mut CybtFwCb, hfd: &mut HexFileData)
0 0
} }
pub(crate) async fn upload_bluetooth_firmware<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>, firmware: &[u8]) { pub(crate) async fn upload_bluetooth_firmware<PWR: OutputPin, SPI: SpiBusCyw43>(
bus: &mut Bus<PWR, SPI>,
firmware: &[u8],
) {
// read version // read version
let version_length = firmware[0]; let version_length = firmware[0];
let _version = &firmware[1..=version_length as usize]; let _version = &firmware[1..=version_length as usize];
// skip version + 1 extra byte as per cybt_shared_bus_driver.c // skip version + 1 extra byte as per cybt_shared_bus_driver.c
let firmware = &firmware[version_length as usize + 2..]; let firmware = &firmware[version_length as usize + 2..];
// buffer // buffer
let mut data_buffer: [u8; 0x100] = [0; 0x100]; let mut data_buffer: [u8; 0x100] = [0; 0x100];
// structs // structs
let mut btfw_cb = CybtFwCb { let mut btfw_cb = CybtFwCb {
p_fw_mem_start: firmware, p_fw_mem_start: firmware,
@ -176,7 +183,7 @@ pub(crate) async fn wait_bt_ready<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bu
} }
pub(crate) async fn wait_bt_awake<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) { pub(crate) async fn wait_bt_awake<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) {
debug!("wait_bt_awake"); debug!("wait_bt_awake");
loop { loop {
let val = bus.bp_read32(BT_CTRL_REG_ADDR).await; let val = bus.bp_read32(BT_CTRL_REG_ADDR).await;
// TODO: do we need to swap endianness on this read? // TODO: do we need to swap endianness on this read?
@ -189,7 +196,7 @@ pub(crate) async fn wait_bt_awake<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bu
} }
pub(crate) async fn bt_set_host_ready<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) { pub(crate) async fn bt_set_host_ready<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) {
debug!("bt_set_host_ready"); debug!("bt_set_host_ready");
let old_val = bus.bp_read32(HOST_CTRL_REG_ADDR).await; let old_val = bus.bp_read32(HOST_CTRL_REG_ADDR).await;
// TODO: do we need to swap endianness on this read? // TODO: do we need to swap endianness on this read?
let new_val = old_val | BTSDIO_REG_SW_RDY_BITMASK; let new_val = old_val | BTSDIO_REG_SW_RDY_BITMASK;
@ -197,7 +204,7 @@ pub(crate) async fn bt_set_host_ready<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mu
} }
pub(crate) async fn bt_set_awake<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) { pub(crate) async fn bt_set_awake<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) {
debug!("bt_set_awake"); debug!("bt_set_awake");
let old_val = bus.bp_read32(HOST_CTRL_REG_ADDR).await; let old_val = bus.bp_read32(HOST_CTRL_REG_ADDR).await;
// TODO: do we need to swap endianness on this read? // TODO: do we need to swap endianness on this read?
let new_val = old_val | BTSDIO_REG_WAKE_BT_BITMASK; let new_val = old_val | BTSDIO_REG_WAKE_BT_BITMASK;
@ -205,7 +212,7 @@ pub(crate) async fn bt_set_awake<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus
} }
pub(crate) async fn bt_toggle_intr<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) { pub(crate) async fn bt_toggle_intr<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) {
debug!("bt_toggle_intr"); debug!("bt_toggle_intr");
let old_val = bus.bp_read32(HOST_CTRL_REG_ADDR).await; let old_val = bus.bp_read32(HOST_CTRL_REG_ADDR).await;
// TODO: do we need to swap endianness on this read? // TODO: do we need to swap endianness on this read?
let new_val = old_val ^ BTSDIO_REG_DATA_VALID_BITMASK; let new_val = old_val ^ BTSDIO_REG_DATA_VALID_BITMASK;
@ -213,14 +220,15 @@ pub(crate) async fn bt_toggle_intr<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut B
} }
pub(crate) async fn bt_set_intr<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) { pub(crate) async fn bt_set_intr<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>) {
debug!("bt_set_intr"); debug!("bt_set_intr");
let old_val = bus.bp_read32(HOST_CTRL_REG_ADDR).await; let old_val = bus.bp_read32(HOST_CTRL_REG_ADDR).await;
let new_val = old_val | BTSDIO_REG_DATA_VALID_BITMASK; let new_val = old_val | BTSDIO_REG_DATA_VALID_BITMASK;
bus.bp_write32(HOST_CTRL_REG_ADDR, new_val).await; bus.bp_write32(HOST_CTRL_REG_ADDR, new_val).await;
} }
pub(crate) async fn init_bluetooth<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>, firmware: &[u8]) { pub(crate) async fn init_bluetooth<PWR: OutputPin, SPI: SpiBusCyw43>(bus: &mut Bus<PWR, SPI>, firmware: &[u8]) {
bus.bp_write32(CHIP.bluetooth_base_address + BT2WLAN_PWRUP_ADDR, BT2WLAN_PWRUP_WAKE).await; bus.bp_write32(CHIP.bluetooth_base_address + BT2WLAN_PWRUP_ADDR, BT2WLAN_PWRUP_WAKE)
.await;
upload_bluetooth_firmware(bus, firmware).await; upload_bluetooth_firmware(bus, firmware).await;
wait_bt_ready(bus).await; wait_bt_ready(bus).await;
// TODO: cybt_init_buffer(); // TODO: cybt_init_buffer();

25
cyw43/src/bus.rs
View File

@ -101,19 +101,34 @@ where
// TODO: setting this causes total failure (watermark read test fails) // TODO: setting this causes total failure (watermark read test fails)
debug!("write SPI_RESP_DELAY_F1 CYW43_BACKPLANE_READ_PAD_LEN_BYTES"); debug!("write SPI_RESP_DELAY_F1 CYW43_BACKPLANE_READ_PAD_LEN_BYTES");
self.write8(FUNC_BUS, SPI_RESP_DELAY_F1, WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE).await; self.write8(FUNC_BUS, SPI_RESP_DELAY_F1, WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE)
.await;
// TODO: Make sure error interrupt bits are clear? // TODO: Make sure error interrupt bits are clear?
// cyw43_write_reg_u8(self, BUS_FUNCTION, SPI_INTERRUPT_REGISTER, DATA_UNAVAILABLE | COMMAND_ERROR | DATA_ERROR | F1_OVERFLOW) != 0) // cyw43_write_reg_u8(self, BUS_FUNCTION, SPI_INTERRUPT_REGISTER, DATA_UNAVAILABLE | COMMAND_ERROR | DATA_ERROR | F1_OVERFLOW) != 0)
debug!("Make sure error interrupt bits are clear"); debug!("Make sure error interrupt bits are clear");
self.write8(FUNC_BUS, REG_BUS_INTERRUPT, (IRQ_DATA_UNAVAILABLE | IRQ_COMMAND_ERROR | IRQ_DATA_ERROR | IRQ_F1_OVERFLOW) as u8) self.write8(
.await; FUNC_BUS,
REG_BUS_INTERRUPT,
(IRQ_DATA_UNAVAILABLE | IRQ_COMMAND_ERROR | IRQ_DATA_ERROR | IRQ_F1_OVERFLOW) as u8,
)
.await;
// Enable a selection of interrupts // Enable a selection of interrupts
// TODO: why not all of these F2_F3_FIFO_RD_UNDERFLOW | F2_F3_FIFO_WR_OVERFLOW | COMMAND_ERROR | DATA_ERROR | F2_PACKET_AVAILABLE | F1_OVERFLOW | F1_INTR // TODO: why not all of these F2_F3_FIFO_RD_UNDERFLOW | F2_F3_FIFO_WR_OVERFLOW | COMMAND_ERROR | DATA_ERROR | F2_PACKET_AVAILABLE | F1_OVERFLOW | F1_INTR
debug!("enable a selection of interrupts"); debug!("enable a selection of interrupts");
self.write16(FUNC_BUS, REG_BUS_INTERRUPT_ENABLE, IRQ_F2_F3_FIFO_RD_UNDERFLOW | IRQ_F2_F3_FIFO_WR_OVERFLOW | IRQ_COMMAND_ERROR | IRQ_DATA_ERROR | IRQ_F2_PACKET_AVAILABLE | IRQ_F1_OVERFLOW | IRQ_F1_INTR) self.write16(
.await; FUNC_BUS,
REG_BUS_INTERRUPT_ENABLE,
IRQ_F2_F3_FIFO_RD_UNDERFLOW
| IRQ_F2_F3_FIFO_WR_OVERFLOW
| IRQ_COMMAND_ERROR
| IRQ_DATA_ERROR
| IRQ_F2_PACKET_AVAILABLE
| IRQ_F1_OVERFLOW
| IRQ_F1_INTR,
)
.await;
} }
pub async fn wlan_read(&mut self, buf: &mut [u32], len_in_u8: u32) { pub async fn wlan_read(&mut self, buf: &mut [u32], len_in_u8: u32) {

10
cyw43/src/consts.rs
View File

@ -51,12 +51,12 @@ pub(crate) const REG_BACKPLANE_READ_FRAME_BC_HIGH: u32 = 0x1001C;
pub(crate) const REG_BACKPLANE_WAKEUP_CTRL: u32 = 0x1001E; pub(crate) const REG_BACKPLANE_WAKEUP_CTRL: u32 = 0x1001E;
pub(crate) const REG_BACKPLANE_SLEEP_CSR: u32 = 0x1001F; pub(crate) const REG_BACKPLANE_SLEEP_CSR: u32 = 0x1001F;
pub(crate) const I_HMB_SW_MASK: u32 = (0x000000f0); pub(crate) const I_HMB_SW_MASK: u32 = (0x000000f0);
pub(crate) const I_HMB_FC_CHANGE: u32 = (1 << 5); pub(crate) const I_HMB_FC_CHANGE: u32 = (1 << 5);
pub(crate) const SDIO_INT_STATUS: u32 = 0x20; pub(crate) const SDIO_INT_STATUS: u32 = 0x20;
pub(crate) const SDIO_INT_HOST_MASK: u32 = 0x24; pub(crate) const SDIO_INT_HOST_MASK: u32 = 0x24;
pub(crate) const SPI_F2_WATERMARK: u8 = 0x20; pub(crate) const SPI_F2_WATERMARK: u8 = 0x20;
pub(crate) const BACKPLANE_WINDOW_SIZE: usize = 0x8000; pub(crate) const BACKPLANE_WINDOW_SIZE: usize = 0x8000;
pub(crate) const BACKPLANE_ADDRESS_MASK: u32 = 0x7FFF; pub(crate) const BACKPLANE_ADDRESS_MASK: u32 = 0x7FFF;

4
cyw43/src/lib.rs
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@ -7,8 +7,8 @@
// This mod MUST go first, so that the others see its macros. // This mod MUST go first, so that the others see its macros.
pub(crate) mod fmt; pub(crate) mod fmt;
mod bus;
mod bluetooth; mod bluetooth;
mod bus;
mod consts; mod consts;
mod countries; mod countries;
mod events; mod events;
@ -214,7 +214,7 @@ pub async fn new<'a, PWR, SPI>(
pwr: PWR, pwr: PWR,
spi: SPI, spi: SPI,
firmware: &[u8], firmware: &[u8],
bluetooth_firmware: &[u8] bluetooth_firmware: &[u8],
) -> (NetDriver<'a>, Control<'a>, Runner<'a, PWR, SPI>) ) -> (NetDriver<'a>, Control<'a>, Runner<'a, PWR, SPI>)
where where
PWR: OutputPin, PWR: OutputPin,

22
cyw43/src/runner.rs
View File

@ -6,13 +6,13 @@ use embedded_hal_1::digital::OutputPin;
use crate::bus::Bus; use crate::bus::Bus;
pub use crate::bus::SpiBusCyw43; pub use crate::bus::SpiBusCyw43;
use crate::{consts::*, bluetooth}; use crate::consts::*;
use crate::events::{Event, Events, Status}; use crate::events::{Event, Events, Status};
use crate::fmt::Bytes; use crate::fmt::Bytes;
use crate::ioctl::{IoctlState, IoctlType, PendingIoctl}; use crate::ioctl::{IoctlState, IoctlType, PendingIoctl};
use crate::nvram::NVRAM; use crate::nvram::NVRAM;
use crate::structs::*; use crate::structs::*;
use crate::{events, slice8_mut, Core, CHIP, MTU}; use crate::{bluetooth, events, slice8_mut, Core, CHIP, MTU};
#[cfg(feature = "firmware-logs")] #[cfg(feature = "firmware-logs")]
struct LogState { struct LogState {
@ -90,7 +90,7 @@ where
let watermark = self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_FUNCTION2_WATERMARK).await; let watermark = self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_FUNCTION2_WATERMARK).await;
debug!("watermark = {:02x}", watermark); debug!("watermark = {:02x}", watermark);
assert!(watermark == 0x10); assert!(watermark == 0x10);
debug!("waiting for clock..."); debug!("waiting for clock...");
while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & BACKPLANE_ALP_AVAIL == 0 {} while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & BACKPLANE_ALP_AVAIL == 0 {}
debug!("clock ok"); debug!("clock ok");
@ -143,16 +143,20 @@ where
// "Set up the interrupt mask and enable interrupts" // "Set up the interrupt mask and enable interrupts"
debug!("setup interrupt mask"); debug!("setup interrupt mask");
self.bus.bp_write32(CHIP.sdiod_core_base_address + SDIO_INT_HOST_MASK, I_HMB_SW_MASK).await; self.bus
.bp_write32(CHIP.sdiod_core_base_address + SDIO_INT_HOST_MASK, I_HMB_SW_MASK)
.await;
// Set up the interrupt mask and enable interrupts // Set up the interrupt mask and enable interrupts
debug!("bluetooth setup interrupt mask"); debug!("bluetooth setup interrupt mask");
self.bus.bp_write32(CHIP.sdiod_core_base_address + SDIO_INT_HOST_MASK, I_HMB_FC_CHANGE).await; self.bus
.bp_write32(CHIP.sdiod_core_base_address + SDIO_INT_HOST_MASK, I_HMB_FC_CHANGE)
.await;
// TODO: turn interrupts on here or in bus.init()? // TODO: turn interrupts on here or in bus.init()?
/*self.bus /*self.bus
.write16(FUNC_BUS, REG_BUS_INTERRUPT_ENABLE, IRQ_F2_PACKET_AVAILABLE) .write16(FUNC_BUS, REG_BUS_INTERRUPT_ENABLE, IRQ_F2_PACKET_AVAILABLE)
.await;*/ .await;*/
// "Lower F2 Watermark to avoid DMA Hang in F2 when SD Clock is stopped." // "Lower F2 Watermark to avoid DMA Hang in F2 when SD Clock is stopped."
// Sounds scary... // Sounds scary...
@ -187,7 +191,9 @@ where
let _ = self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_PULL_UP).await; let _ = self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_PULL_UP).await;
// start HT clock // start HT clock
self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x10).await; // SBSDIO_HT_AVAIL_REQ self.bus
.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x10)
.await; // SBSDIO_HT_AVAIL_REQ
debug!("waiting for HT clock..."); debug!("waiting for HT clock...");
while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & 0x80 == 0 {} while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & 0x80 == 0 {}
debug!("clock ok"); debug!("clock ok");