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fix typo, minor cleanup

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This commit is contained in:
JuliDi 2023-06-19 13:50:17 +02:00
parent 218b102b28
commit 88052480b1
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GPG Key ID: E1E90AE563D09D63
2 changed files with 10 additions and 10 deletions
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13
embassy-stm32/src/dac/mod.rs
View File

@ -275,42 +275,43 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
}); });
let tx_request = self.txdma.request(); let tx_request = self.txdma.request();
let channel = &mut self.txdma;
// Initiate the correct type of DMA transfer depending on what data is passed // Initiate the correct type of DMA transfer depending on what data is passed
let tx_f = match data_ch1 { let tx_f = match data_ch1 {
ValueArray::Bit8(buf) => unsafe { ValueArray::Bit8(buf) => unsafe {
Transfer::new_write( Transfer::new_write(
&mut self.txdma, channel,
tx_request, tx_request,
buf, buf,
T::regs().dhr8r(CHANNEL).as_ptr() as *mut u8, T::regs().dhr8r(CHANNEL).as_ptr() as *mut u8,
TransferOptions { TransferOptions {
circular, circular,
halt_transfer_ir: false, half_transfer_ir: false,
}, },
) )
}, },
ValueArray::Bit12Left(buf) => unsafe { ValueArray::Bit12Left(buf) => unsafe {
Transfer::new_write( Transfer::new_write(
&mut self.txdma, channel,
tx_request, tx_request,
buf, buf,
T::regs().dhr12l(CHANNEL).as_ptr() as *mut u16, T::regs().dhr12l(CHANNEL).as_ptr() as *mut u16,
TransferOptions { TransferOptions {
circular, circular,
halt_transfer_ir: false, half_transfer_ir: false,
}, },
) )
}, },
ValueArray::Bit12Right(buf) => unsafe { ValueArray::Bit12Right(buf) => unsafe {
Transfer::new_write( Transfer::new_write(
&mut self.txdma, channel,
tx_request, tx_request,
buf, buf,
T::regs().dhr12r(CHANNEL).as_ptr() as *mut u16, T::regs().dhr12r(CHANNEL).as_ptr() as *mut u16,
TransferOptions { TransferOptions {
circular, circular,
halt_transfer_ir: false, half_transfer_ir: false,
}, },
) )
}, },

7
embassy-stm32/src/dma/bdma.rs
View File

@ -1,7 +1,6 @@
#![macro_use] #![macro_use]
use core::future::Future; use core::future::Future;
use core::option;
use core::pin::Pin; use core::pin::Pin;
use core::sync::atomic::{fence, Ordering}; use core::sync::atomic::{fence, Ordering};
use core::task::{Context, Poll, Waker}; use core::task::{Context, Poll, Waker};
@ -24,14 +23,14 @@ use crate::pac::bdma::{regs, vals};
#[non_exhaustive] #[non_exhaustive]
pub struct TransferOptions { pub struct TransferOptions {
pub circular: bool, pub circular: bool,
pub halt_transfer_ir: bool, pub half_transfer_ir: bool,
} }
impl Default for TransferOptions { impl Default for TransferOptions {
fn default() -> Self { fn default() -> Self {
Self { Self {
circular: false, circular: false,
halt_transfer_ir: false, half_transfer_ir: false,
} }
} }
} }
@ -291,7 +290,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
w.set_dir(dir.into()); w.set_dir(dir.into());
w.set_teie(true); w.set_teie(true);
w.set_tcie(true); w.set_tcie(true);
w.set_htie(options.halt_transfer_ir); w.set_htie(options.half_transfer_ir);
if options.circular { if options.circular {
w.set_circ(vals::Circ::ENABLED); w.set_circ(vals::Circ::ENABLED);
debug!("Setting circular mode"); debug!("Setting circular mode");