usb: add first, last params to ControlPipe data_in, data_out.
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@ -657,7 +657,12 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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}
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}
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fn data_out<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::DataOutFuture<'a> {
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fn data_out<'a>(
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&'a mut self,
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buf: &'a mut [u8],
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_first: bool,
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_last: bool,
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) -> Self::DataOutFuture<'a> {
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async move {
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let regs = T::regs();
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@ -694,13 +699,17 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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}
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}
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fn data_in<'a>(&'a mut self, buf: &'a [u8], last_packet: bool) -> Self::DataInFuture<'a> {
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fn data_in<'a>(
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&'a mut self,
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buf: &'a [u8],
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_first: bool,
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last: bool,
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) -> Self::DataInFuture<'a> {
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async move {
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let regs = T::regs();
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regs.events_ep0datadone.reset();
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regs.shorts
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.write(|w| w.ep0datadone_ep0status().bit(last_packet));
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regs.shorts.write(|w| w.ep0datadone_ep0status().bit(last));
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// This starts a TX on EP0. events_ep0datadone notifies when done.
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unsafe { write_dma::<T>(0, buf) }
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