usb: add first, last params to ControlPipe data_in, data_out.
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1ec2e5672f
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@ -657,7 +657,12 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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}
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}
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fn data_out<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::DataOutFuture<'a> {
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fn data_out<'a>(
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&'a mut self,
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buf: &'a mut [u8],
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_first: bool,
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_last: bool,
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) -> Self::DataOutFuture<'a> {
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async move {
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let regs = T::regs();
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@ -694,13 +699,17 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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}
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}
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fn data_in<'a>(&'a mut self, buf: &'a [u8], last_packet: bool) -> Self::DataInFuture<'a> {
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fn data_in<'a>(
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&'a mut self,
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buf: &'a [u8],
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_first: bool,
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last: bool,
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) -> Self::DataInFuture<'a> {
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async move {
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let regs = T::regs();
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regs.events_ep0datadone.reset();
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regs.shorts
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.write(|w| w.ep0datadone_ep0status().bit(last_packet));
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regs.shorts.write(|w| w.ep0datadone_ep0status().bit(last));
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// This starts a TX on EP0. events_ep0datadone notifies when done.
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unsafe { write_dma::<T>(0, buf) }
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@ -155,12 +155,18 @@ pub trait ControlPipe {
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///
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/// Must be called after `setup()` for requests with `direction` of `Out`
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/// and `length` greater than zero.
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fn data_out<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::DataOutFuture<'a>;
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fn data_out<'a>(
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&'a mut self,
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buf: &'a mut [u8],
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first: bool,
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last: bool,
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) -> Self::DataOutFuture<'a>;
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/// Sends a DATA IN packet with `data` in response to a control read request.
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///
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/// If `last_packet` is true, the STATUS packet will be ACKed following the transfer of `data`.
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fn data_in<'a>(&'a mut self, data: &'a [u8], last_packet: bool) -> Self::DataInFuture<'a>;
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fn data_in<'a>(&'a mut self, data: &'a [u8], first: bool, last: bool)
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-> Self::DataInFuture<'a>;
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/// Accepts a control request.
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///
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@ -292,12 +292,12 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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let len = data.len().min(resp_length);
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let need_zlp = len != resp_length && (len % usize::from(max_packet_size)) == 0;
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let mut chunks = data[0..len]
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let chunks = data[0..len]
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.chunks(max_packet_size)
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.chain(need_zlp.then(|| -> &[u8] { &[] }));
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while let Some(chunk) = chunks.next() {
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match self.control.data_in(chunk, chunks.size_hint().0 == 0).await {
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for (first, last, chunk) in first_last(chunks) {
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match self.control.data_in(chunk, first, last).await {
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Ok(()) => {}
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Err(e) => {
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warn!("control accept_in failed: {:?}", e);
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@ -315,8 +315,9 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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let max_packet_size = self.control.max_packet_size();
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let mut total = 0;
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for chunk in self.control_buf[..req_length].chunks_mut(max_packet_size) {
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let size = match self.control.data_out(chunk).await {
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let chunks = self.control_buf[..req_length].chunks_mut(max_packet_size);
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for (first, last, chunk) in first_last(chunks) {
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let size = match self.control.data_out(chunk, first, last).await {
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Ok(x) => x,
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Err(e) => {
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warn!("usb: failed to read CONTROL OUT data stage: {:?}", e);
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@ -668,3 +669,15 @@ impl<'d, D: Driver<'d>> Inner<'d, D> {
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}
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}
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}
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fn first_last<T: Iterator>(iter: T) -> impl Iterator<Item = (bool, bool, T::Item)> {
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let mut iter = iter.peekable();
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let mut first = true;
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core::iter::from_fn(move || {
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let val = iter.next()?;
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let is_first = first;
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first = false;
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let is_last = iter.peek().is_none();
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Some((is_first, is_last, val))
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})
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}
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