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F4: Fix compilation for other MCUs

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This commit is contained in:
Thales Fragoso
2021-03-18 22:23:09 -03:00
parent 456e04c79f
commit 88a25b042a
9 changed files with 80 additions and 19 deletions
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4
embassy-stm32f4/src/can.rs
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@ -42,7 +42,8 @@ impl<T: Instance> Can<T> {
pub fn transmit<'a>(&'a mut self, frame: &'a bxcan::Frame) -> impl Future<Output = ()> + 'a {
async move {
let fut = InterruptFuture::new(&mut self.tx_int);
self.can.transmit(frame);
// Infallible
self.can.transmit(frame).unwrap();
fut.await;
}
@ -94,7 +95,6 @@ macro_rules! can {
}
}
#[cfg(any(feature = "stm32f405",))]
can! {
CAN1 => (CAN1_TX, CAN1_RX0),
CAN2 => (CAN2_TX, CAN2_RX0),

1
embassy-stm32f4/src/exti.rs
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@ -1,4 +1,3 @@
use core::cell::UnsafeCell;
use core::future::Future;
use core::mem;
use core::pin::Pin;

2
embassy-stm32f4/src/lib.rs
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@ -313,9 +313,11 @@ pub use stm32f4xx_hal::stm32 as pac;
// This mod MUST go first, so that the others see its macros.
pub(crate) mod fmt;
#[cfg(not(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411",)))]
pub mod can;
pub mod exti;
pub mod interrupt;
#[cfg(not(feature = "stm32f410"))]
pub mod qei;
pub mod rtc;
pub mod serial;

6
embassy-stm32f4/src/qei.rs
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@ -7,7 +7,7 @@ use stm32f4xx_hal::pac::TIM2;
use stm32f4xx_hal::{qei, qei::Pins};
pub struct Qei<T: Instance, PINS> {
qei: qei::Qei<T, PINS>,
_qei: qei::Qei<T, PINS>,
int: T::Interrupt,
}
@ -25,7 +25,7 @@ impl<PINS: Pins<TIM2>> Qei<TIM2, PINS> {
tim.dier.write(|w| w.uie().set_bit());
Qei {
qei: qei,
_qei: qei,
int: interrupt,
}
}
@ -85,9 +85,7 @@ pub trait Instance: sealed::Sealed {
type Interrupt: interrupt::Interrupt;
}
#[cfg(feature = "stm32f405")]
impl sealed::Sealed for TIM2 {}
#[cfg(feature = "stm32f405")]
impl Instance for TIM2 {
type Interrupt = interrupt::TIM2;
}

56
embassy-stm32f4/src/serial.rs
View File

@ -6,7 +6,6 @@
use core::future::Future;
use core::marker::PhantomData;
use core::sync::atomic::{self, Ordering};
use embassy::interrupt::Interrupt;
use embassy::traits::uart::{Error, Uart};
@ -37,7 +36,7 @@ pub struct Serial<
usart: Option<USART>,
tx_int: TSTREAM::Interrupt,
rx_int: RSTREAM::Interrupt,
usart_int: USART::Interrupt,
_usart_int: USART::Interrupt,
channel: PhantomData<CHANNEL>,
}
@ -84,7 +83,7 @@ where
usart: Some(usart),
tx_int: tx_int,
rx_int: rx_int,
usart_int: usart_int,
_usart_int: usart_int,
channel: core::marker::PhantomData,
}
}
@ -207,7 +206,6 @@ macro_rules! usart {
}
}
#[cfg(any(feature = "stm32f405",))]
dma! {
DMA2_STREAM0 => (DMA2, Stream0),
DMA2_STREAM1 => (DMA2, Stream1),
@ -226,12 +224,60 @@ dma! {
DMA1_STREAM6 => (DMA1, Stream6),
}
#[cfg(any(feature = "stm32f405",))]
#[cfg(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411",))]
usart! {
USART1 => (USART1),
USART2 => (USART2),
USART6 => (USART6),
}
#[cfg(any(feature = "stm32f405", feature = "stm32f407"))]
usart! {
USART1 => (USART1),
USART2 => (USART2),
USART3 => (USART3),
USART6 => (USART6),
UART4 => (UART4),
UART5 => (UART5),
}
#[cfg(feature = "stm32f412")]
usart! {
USART1 => (USART1),
USART2 => (USART2),
USART3 => (USART3),
USART6 => (USART6),
}
#[cfg(feature = "stm32f413")]
usart! {
USART1 => (USART1),
USART2 => (USART2),
USART3 => (USART3),
USART6 => (USART6),
USART7 => (USART7),
USART8 => (USART8),
UART5 => (UART5),
UART9 => (UART9),
UART10 => (UART10),
}
#[cfg(any(
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469"
))]
usart! {
USART1 => (USART1),
USART2 => (USART2),
USART3 => (USART3),
USART6 => (USART6),
UART4 => (UART4),
UART5 => (UART5),
UART7 => (UART7),
UART8 => (UART8),
}