From e892014b6572e74b58ea653cfed06614c496e6a5 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Thu, 29 Jun 2023 01:51:19 +0200 Subject: [PATCH] Update stm32-metapac, includes chiptool changes to use real Rust enums now. --- embassy-stm32/Cargo.toml | 4 +- embassy-stm32/src/adc/v3.rs | 8 ++-- embassy-stm32/src/can/bxcan.rs | 8 ++-- embassy-stm32/src/eth/v1/rx_desc.rs | 2 +- embassy-stm32/src/pwm/complementary_pwm.rs | 2 +- embassy-stm32/src/rcc/c0.rs | 10 ++-- embassy-stm32/src/rcc/f0.rs | 23 +++++---- embassy-stm32/src/rcc/f1.rs | 36 +++++++------- embassy-stm32/src/rcc/f2.rs | 2 +- embassy-stm32/src/rcc/f4.rs | 12 ++--- embassy-stm32/src/rcc/f7.rs | 12 ++--- embassy-stm32/src/rcc/g0.rs | 10 ++-- embassy-stm32/src/rcc/h7.rs | 17 +++---- embassy-stm32/src/rcc/l0.rs | 6 +-- embassy-stm32/src/rcc/l1.rs | 6 +-- embassy-stm32/src/rcc/l4.rs | 6 +-- embassy-stm32/src/rcc/l5.rs | 6 +-- embassy-stm32/src/rcc/u5.rs | 2 +- embassy-stm32/src/rtc/v2.rs | 4 +- embassy-stm32/src/rtc/v3.rs | 2 +- embassy-stm32/src/spi/mod.rs | 4 +- embassy-stm32/src/usart/mod.rs | 2 +- embassy-stm32/src/usb/usb.rs | 56 +++++++++++----------- embassy-stm32/src/usb_otg/usb.rs | 4 +- embassy-stm32/src/wdg/mod.rs | 2 +- 25 files changed, 121 insertions(+), 125 deletions(-) diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index f15c6d0b..b3fe9c1f 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -57,7 +57,7 @@ sdio-host = "0.5.0" embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true } critical-section = "1.1" atomic-polyfill = "1.0.1" -stm32-metapac = "11" +stm32-metapac = "12" vcell = "0.1.3" bxcan = "0.7.0" nb = "1.0.0" @@ -74,7 +74,7 @@ critical-section = { version = "1.1", features = ["std"] } [build-dependencies] proc-macro2 = "1.0.36" quote = "1.0.15" -stm32-metapac = { version = "11", default-features = false, features = ["metadata"]} +stm32-metapac = { version = "12", default-features = false, features = ["metadata"]} [features] default = ["rt"] diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 94cdc86c..3a6e58cf 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -211,10 +211,8 @@ impl<'d, T: Instance> Adc<'d, T> { #[cfg(not(stm32g0))] fn set_channel_sample_time(ch: u8, sample_time: SampleTime) { let sample_time = sample_time.into(); - if ch <= 9 { - T::regs().smpr1().modify(|reg| reg.set_smp(ch as _, sample_time)); - } else { - T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time)); - } + T::regs() + .smpr(ch as usize / 10) + .modify(|reg| reg.set_smp(ch as usize % 10, sample_time)); } } diff --git a/embassy-stm32/src/can/bxcan.rs b/embassy-stm32/src/can/bxcan.rs index 88eef528..73861776 100644 --- a/embassy-stm32/src/can/bxcan.rs +++ b/embassy-stm32/src/can/bxcan.rs @@ -116,10 +116,10 @@ impl<'d, T: Instance> Can<'d, T> { T::regs().ier().write(|w| { // TODO: fix metapac - w.set_errie(Errie(1)); - w.set_fmpie(0, Fmpie(1)); - w.set_fmpie(1, Fmpie(1)); - w.set_tmeie(Tmeie(1)); + w.set_errie(Errie::from_bits(1)); + w.set_fmpie(0, Fmpie::from_bits(1)); + w.set_fmpie(1, Fmpie::from_bits(1)); + w.set_tmeie(Tmeie::from_bits(1)); }); T::regs().mcr().write(|w| { diff --git a/embassy-stm32/src/eth/v1/rx_desc.rs b/embassy-stm32/src/eth/v1/rx_desc.rs index 01a073bb..668378be 100644 --- a/embassy-stm32/src/eth/v1/rx_desc.rs +++ b/embassy-stm32/src/eth/v1/rx_desc.rs @@ -174,7 +174,7 @@ impl<'a> RDesRing<'a> { // Receive descriptor unavailable Rps::SUSPENDED => RunningState::Stopped, // Closing receive descriptor - Rps(0b101) => RunningState::Running, + Rps::_RESERVED_5 => RunningState::Running, // Transferring the receive packet data from receive buffer to host memory Rps::RUNNINGWRITING => RunningState::Running, _ => RunningState::Unknown, diff --git a/embassy-stm32/src/pwm/complementary_pwm.rs b/embassy-stm32/src/pwm/complementary_pwm.rs index 0e153202..4d64d005 100644 --- a/embassy-stm32/src/pwm/complementary_pwm.rs +++ b/embassy-stm32/src/pwm/complementary_pwm.rs @@ -243,7 +243,7 @@ mod tests { for test_run in fn_results { let (ckd, bits) = compute_dead_time_value(test_run.value); - assert_eq!(ckd.0, test_run.ckd.0); + assert_eq!(ckd.to_bits(), test_run.ckd.to_bits()); assert_eq!(bits, test_run.bits); } } diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs index 6c7b3664..df6e9047 100644 --- a/embassy-stm32/src/rcc/c0.rs +++ b/embassy-stm32/src/rcc/c0.rs @@ -126,7 +126,7 @@ pub(crate) unsafe fn init(config: Config) { }); while !RCC.cr().read().hsirdy() {} - (HSI_FREQ.0 >> div.0, Sw::HSI) + (HSI_FREQ.0 >> div.to_bits(), Sw::HSI) } ClockSrc::HSE(freq) => { // Enable HSE @@ -157,7 +157,7 @@ pub(crate) unsafe fn init(config: Config) { let mut set_flash_latency_after = false; FLASH.acr().modify(|w| { // Is the current flash latency less than what we need at the new SYSCLK? - if w.latency().0 <= target_flash_latency.0 { + if w.latency().to_bits() <= target_flash_latency.to_bits() { // We must increase the number of wait states now w.set_latency(target_flash_latency) } else { @@ -171,12 +171,12 @@ pub(crate) unsafe fn init(config: Config) { // > Flash memory. // // Enable flash prefetching if we have at least one wait state, and disable it otherwise. - w.set_prften(target_flash_latency.0 > 0); + w.set_prften(target_flash_latency.to_bits() > 0); }); if !set_flash_latency_after { // Spin until the effective flash latency is compatible with the clock change - while FLASH.acr().read().latency().0 < target_flash_latency.0 {} + while FLASH.acr().read().latency().to_bits() < target_flash_latency.to_bits() {} } // Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once @@ -218,7 +218,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs index eb62ab66..ca6eed28 100644 --- a/embassy-stm32/src/rcc/f0.rs +++ b/embassy-stm32/src/rcc/f0.rs @@ -1,3 +1,5 @@ +use stm32_metapac::flash::vals::Latency; + use super::{set_freqs, Clocks}; use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw}; use crate::pac::{FLASH, RCC}; @@ -85,14 +87,11 @@ pub(crate) unsafe fn init(config: Config) { let timer_mul = if ppre == 1 { 1 } else { 2 }; FLASH.acr().write(|w| { - let latency = if real_sysclk <= 24_000_000 { - 0 - } else if real_sysclk <= 48_000_000 { - 1 + w.set_latency(if real_sysclk <= 24_000_000 { + Latency::WS0 } else { - 2 - }; - w.latency().0 = latency; + Latency::WS1 + }); }); match (config.hse.is_some(), use_hsi48) { @@ -134,20 +133,20 @@ pub(crate) unsafe fn init(config: Config) { // TODO: Option to use CRS (Clock Recovery) if let Some(pllmul_bits) = pllmul_bits { - RCC.cfgr().modify(|w| w.set_pllmul(Pllmul(pllmul_bits))); + RCC.cfgr().modify(|w| w.set_pllmul(Pllmul::from_bits(pllmul_bits))); RCC.cr().modify(|w| w.set_pllon(true)); while !RCC.cr().read().pllrdy() {} RCC.cfgr().modify(|w| { - w.set_ppre(Ppre(ppre_bits)); - w.set_hpre(Hpre(hpre_bits)); + w.set_ppre(Ppre::from_bits(ppre_bits)); + w.set_hpre(Hpre::from_bits(hpre_bits)); w.set_sw(Sw::PLL) }); } else { RCC.cfgr().modify(|w| { - w.set_ppre(Ppre(ppre_bits)); - w.set_hpre(Hpre(hpre_bits)); + w.set_ppre(Ppre::from_bits(ppre_bits)); + w.set_hpre(Hpre::from_bits(hpre_bits)); if config.hse.is_some() { w.set_sw(Sw::HSE); diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs index 4769b705..b6200231 100644 --- a/embassy-stm32/src/rcc/f1.rs +++ b/embassy-stm32/src/rcc/f1.rs @@ -106,11 +106,11 @@ pub(crate) unsafe fn init(config: Config) { // Only needed for stm32f103? FLASH.acr().write(|w| { w.set_latency(if real_sysclk <= 24_000_000 { - Latency(0b000) + Latency::WS0 } else if real_sysclk <= 48_000_000 { - Latency(0b001) + Latency::WS1 } else { - Latency(0b010) + Latency::WS2 }); }); @@ -147,12 +147,13 @@ pub(crate) unsafe fn init(config: Config) { if let Some(pllmul_bits) = pllmul_bits { let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 }; - RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag))); + RCC.cfgr() + .modify(|w| w.set_pllxtpre(Pllxtpre::from_bits(pllctpre_flag))); // enable PLL and wait for it to be ready RCC.cfgr().modify(|w| { - w.set_pllmul(Pllmul(pllmul_bits)); - w.set_pllsrc(Pllsrc(config.hse.is_some() as u8)); + w.set_pllmul(Pllmul::from_bits(pllmul_bits)); + w.set_pllsrc(Pllsrc::from_bits(config.hse.is_some() as u8)); }); RCC.cr().modify(|w| w.set_pllon(true)); @@ -161,22 +162,19 @@ pub(crate) unsafe fn init(config: Config) { // Only needed for stm32f103? RCC.cfgr().modify(|w| { - w.set_adcpre(Adcpre(apre_bits)); - w.set_ppre2(Ppre1(ppre2_bits)); - w.set_ppre1(Ppre1(ppre1_bits)); - w.set_hpre(Hpre(hpre_bits)); + w.set_adcpre(Adcpre::from_bits(apre_bits)); + w.set_ppre2(Ppre1::from_bits(ppre2_bits)); + w.set_ppre1(Ppre1::from_bits(ppre1_bits)); + w.set_hpre(Hpre::from_bits(hpre_bits)); #[cfg(not(rcc_f100))] - w.set_usbpre(Usbpre(usbpre as u8)); - w.set_sw(Sw(if pllmul_bits.is_some() { - // PLL - 0b10 + w.set_usbpre(Usbpre::from_bits(usbpre as u8)); + w.set_sw(if pllmul_bits.is_some() { + Sw::PLL } else if config.hse.is_some() { - // HSE - 0b1 + Sw::HSE } else { - // HSI - 0b0 - })); + Sw::HSI + }); }); set_freqs(Clocks { diff --git a/embassy-stm32/src/rcc/f2.rs b/embassy-stm32/src/rcc/f2.rs index bcae64d0..1525cc3c 100644 --- a/embassy-stm32/src/rcc/f2.rs +++ b/embassy-stm32/src/rcc/f2.rs @@ -485,7 +485,7 @@ pub(crate) unsafe fn init(config: Config) { w.set_ppre1(config.apb1_pre.into()); w.set_ppre2(config.apb2_pre.into()); }); - while RCC.cfgr().read().sws() != sw.0 {} + while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {} // Turn off HSI to save power if we don't need it if !config.hsi { diff --git a/embassy-stm32/src/rcc/f4.rs b/embassy-stm32/src/rcc/f4.rs index bc430afb..b8447044 100644 --- a/embassy-stm32/src/rcc/f4.rs +++ b/embassy-stm32/src/rcc/f4.rs @@ -87,7 +87,7 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option, plli2s: Opti let sysclk = pllsysclk.unwrap_or(pllsrcclk); if pllsysclk.is_none() && !pll48clk { - RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8))); + RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8))); return PllResults { use_pll: false, @@ -141,9 +141,9 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option, plli2s: Opti RCC.pllcfgr().modify(|w| { w.set_pllm(pllm as u8); w.set_plln(plln as u16); - w.set_pllp(Pllp(pllp as u8)); + w.set_pllp(Pllp::from_bits(pllp as u8)); w.set_pllq(pllq as u8); - w.set_pllsrc(Pllsrc(use_hse as u8)); + w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)); }); let real_pllsysclk = vco_in * plln / sysclk_div; @@ -323,7 +323,7 @@ fn flash_setup(sysclk: u32) { critical_section::with(|_| { FLASH .acr() - .modify(|w| w.set_latency(Latency(((sysclk - 1) / FLASH_LATENCY_STEP) as u8))); + .modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8))); }); } @@ -440,8 +440,8 @@ pub(crate) unsafe fn init(config: Config) { } RCC.cfgr().modify(|w| { - w.set_ppre2(Ppre(ppre2_bits)); - w.set_ppre1(Ppre(ppre1_bits)); + w.set_ppre2(Ppre::from_bits(ppre2_bits)); + w.set_ppre1(Ppre::from_bits(ppre1_bits)); w.set_hpre(hpre_bits); }); diff --git a/embassy-stm32/src/rcc/f7.rs b/embassy-stm32/src/rcc/f7.rs index 71215cac..85cb9c66 100644 --- a/embassy-stm32/src/rcc/f7.rs +++ b/embassy-stm32/src/rcc/f7.rs @@ -30,7 +30,7 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option, pll48clk: bo let sysclk = pllsysclk.unwrap_or(pllsrcclk); if pllsysclk.is_none() && !pll48clk { - RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8))); + RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8))); return PllResults { use_pll: false, @@ -83,9 +83,9 @@ fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option, pll48clk: bo RCC.pllcfgr().modify(|w| { w.set_pllm(pllm as u8); w.set_plln(plln as u16); - w.set_pllp(Pllp(pllp as u8)); + w.set_pllp(Pllp::from_bits(pllp as u8)); w.set_pllq(pllq as u8); - w.set_pllsrc(Pllsrc(use_hse as u8)); + w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)); }); let real_pllsysclk = vco_in * plln / sysclk_div; @@ -106,7 +106,7 @@ fn flash_setup(sysclk: u32) { critical_section::with(|_| { FLASH .acr() - .modify(|w| w.set_latency(Latency(((sysclk - 1) / FLASH_LATENCY_STEP) as u8))); + .modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8))); }); } @@ -246,8 +246,8 @@ pub(crate) unsafe fn init(config: Config) { } RCC.cfgr().modify(|w| { - w.set_ppre2(Ppre(ppre2_bits)); - w.set_ppre1(Ppre(ppre1_bits)); + w.set_ppre2(Ppre::from_bits(ppre2_bits)); + w.set_ppre1(Ppre::from_bits(ppre1_bits)); w.set_hpre(hpre_bits); }); diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs index 17c73c36..5e3a7911 100644 --- a/embassy-stm32/src/rcc/g0.rs +++ b/embassy-stm32/src/rcc/g0.rs @@ -344,7 +344,7 @@ pub(crate) unsafe fn init(config: Config) { }); while !RCC.cr().read().hsirdy() {} - (HSI_FREQ.0 >> div.0, Sw::HSI) + (HSI_FREQ.0 >> div.to_bits(), Sw::HSI) } ClockSrc::HSE(freq) => { // Enable HSE @@ -381,7 +381,7 @@ pub(crate) unsafe fn init(config: Config) { let mut set_flash_latency_after = false; FLASH.acr().modify(|w| { // Is the current flash latency less than what we need at the new SYSCLK? - if w.latency().0 <= target_flash_latency.0 { + if w.latency().to_bits() <= target_flash_latency.to_bits() { // We must increase the number of wait states now w.set_latency(target_flash_latency) } else { @@ -395,12 +395,12 @@ pub(crate) unsafe fn init(config: Config) { // > Flash memory. // // Enable flash prefetching if we have at least one wait state, and disable it otherwise. - w.set_prften(target_flash_latency.0 > 0); + w.set_prften(target_flash_latency.to_bits() > 0); }); if !set_flash_latency_after { // Spin until the effective flash latency is compatible with the clock change - while FLASH.acr().read().latency().0 < target_flash_latency.0 {} + while FLASH.acr().read().latency().to_bits() < target_flash_latency.to_bits() {} } // Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once @@ -442,7 +442,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } diff --git a/embassy-stm32/src/rcc/h7.rs b/embassy-stm32/src/rcc/h7.rs index daa1cd61..f3a98c79 100644 --- a/embassy-stm32/src/rcc/h7.rs +++ b/embassy-stm32/src/rcc/h7.rs @@ -601,22 +601,22 @@ pub(crate) unsafe fn init(mut config: Config) { // Core Prescaler / AHB Prescaler / APB3 Prescaler RCC.d1cfgr().modify(|w| { - w.set_d1cpre(Hpre(d1cpre_bits)); - w.set_d1ppre(Dppre(ppre3_bits)); + w.set_d1cpre(Hpre::from_bits(d1cpre_bits)); + w.set_d1ppre(Dppre::from_bits(ppre3_bits)); w.set_hpre(hpre_bits) }); // Ensure core prescaler value is valid before future lower // core voltage - while RCC.d1cfgr().read().d1cpre().0 != d1cpre_bits {} + while RCC.d1cfgr().read().d1cpre().to_bits() != d1cpre_bits {} // APB1 / APB2 Prescaler RCC.d2cfgr().modify(|w| { - w.set_d2ppre1(Dppre(ppre1_bits)); - w.set_d2ppre2(Dppre(ppre2_bits)); + w.set_d2ppre1(Dppre::from_bits(ppre1_bits)); + w.set_d2ppre2(Dppre::from_bits(ppre2_bits)); }); // APB4 Prescaler - RCC.d3cfgr().modify(|w| w.set_d3ppre(Dppre(ppre4_bits))); + RCC.d3cfgr().modify(|w| w.set_d3ppre(Dppre::from_bits(ppre4_bits))); // Peripheral Clock (per_ck) RCC.d1ccipr().modify(|w| w.set_ckpersel(ckpersel)); @@ -640,7 +640,7 @@ pub(crate) unsafe fn init(mut config: Config) { _ => Sw::HSI, }; RCC.cfgr().modify(|w| w.set_sw(sw)); - while RCC.cfgr().read().sws() != sw.0 {} + while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {} // IO compensation cell - Requires CSI clock and SYSCFG assert!(RCC.cr().read().csirdy()); @@ -806,7 +806,8 @@ mod pll { RCC.pllcfgr().modify(|w| w.set_pllfracen(plln, false)); let vco_ck = ref_x_ck * pll_x_n; - RCC.plldivr(plln).modify(|w| w.set_divp1(Divp((pll_x_p - 1) as u8))); + RCC.plldivr(plln) + .modify(|w| w.set_divp1(Divp::from_bits((pll_x_p - 1) as u8))); RCC.pllcfgr().modify(|w| w.set_divpen(plln, true)); // Calulate additional output dividers diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0.rs index d53b6106..46a528e3 100644 --- a/embassy-stm32/src/rcc/l0.rs +++ b/embassy-stm32/src/rcc/l0.rs @@ -293,7 +293,7 @@ pub(crate) unsafe fn init(config: Config) { AHBPrescaler::NotDivided => sys_clk, pre => { let pre: Hpre = pre.into(); - let pre = 1 << (pre.0 as u32 - 7); + let pre = 1 << (pre.to_bits() as u32 - 7); sys_clk / pre } }; @@ -302,7 +302,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } @@ -312,7 +312,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } diff --git a/embassy-stm32/src/rcc/l1.rs b/embassy-stm32/src/rcc/l1.rs index c907fa88..59a6eac8 100644 --- a/embassy-stm32/src/rcc/l1.rs +++ b/embassy-stm32/src/rcc/l1.rs @@ -294,7 +294,7 @@ pub(crate) unsafe fn init(config: Config) { AHBPrescaler::NotDivided => sys_clk, pre => { let pre: Hpre = pre.into(); - let pre = 1 << (pre.0 as u32 - 7); + let pre = 1 << (pre.to_bits() as u32 - 7); sys_clk / pre } }; @@ -303,7 +303,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } @@ -313,7 +313,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } diff --git a/embassy-stm32/src/rcc/l4.rs b/embassy-stm32/src/rcc/l4.rs index f8c1a6e0..20cb8c91 100644 --- a/embassy-stm32/src/rcc/l4.rs +++ b/embassy-stm32/src/rcc/l4.rs @@ -635,7 +635,7 @@ pub(crate) unsafe fn init(config: Config) { AHBPrescaler::NotDivided => sys_clk, pre => { let pre: Hpre = pre.into(); - let pre = 1 << (pre.0 as u32 - 7); + let pre = 1 << (pre.to_bits() as u32 - 7); sys_clk / pre } }; @@ -644,7 +644,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } @@ -654,7 +654,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } diff --git a/embassy-stm32/src/rcc/l5.rs b/embassy-stm32/src/rcc/l5.rs index f56fce36..16da65d5 100644 --- a/embassy-stm32/src/rcc/l5.rs +++ b/embassy-stm32/src/rcc/l5.rs @@ -461,7 +461,7 @@ pub(crate) unsafe fn init(config: Config) { AHBPrescaler::NotDivided => sys_clk, pre => { let pre: Hpre = pre.into(); - let pre = 1 << (pre.0 as u32 - 7); + let pre = 1 << (pre.to_bits() as u32 - 7); sys_clk / pre } }; @@ -470,7 +470,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } @@ -480,7 +480,7 @@ pub(crate) unsafe fn init(config: Config) { APBPrescaler::NotDivided => (ahb_freq, ahb_freq), pre => { let pre: Ppre = pre.into(); - let pre: u8 = 1 << (pre.0 - 3); + let pre: u8 = 1 << (pre.to_bits() - 3); let freq = ahb_freq / pre as u32; (freq, freq * 2) } diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs index 81507a4d..cfc07f06 100644 --- a/embassy-stm32/src/rcc/u5.rs +++ b/embassy-stm32/src/rcc/u5.rs @@ -126,7 +126,7 @@ pub enum PllM { impl Into for PllM { fn into(self) -> Pllm { - Pllm(self as u8) + Pllm::from_bits(self as u8) } } diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs index e1615b34..a2eace6d 100644 --- a/embassy-stm32/src/rtc/v2.rs +++ b/embassy-stm32/src/rtc/v2.rs @@ -36,7 +36,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> { #[cfg(rtc_v2wb)] let rtcsel = reg.rtcsel(); #[cfg(not(rtc_v2wb))] - let rtcsel = reg.rtcsel().0; + let rtcsel = reg.rtcsel().to_bits(); if !reg.rtcen() || rtcsel != clock_config { #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] @@ -54,7 +54,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> { // Select RTC source #[cfg(not(rtc_v2wb))] - w.set_rtcsel(Rtcsel(clock_config)); + w.set_rtcsel(Rtcsel::from_bits(clock_config)); #[cfg(rtc_v2wb)] w.set_rtcsel(clock_config); w.set_rtcen(true); diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs index 7c91046a..7e5c64d9 100644 --- a/embassy-stm32/src/rtc/v3.rs +++ b/embassy-stm32/src/rtc/v3.rs @@ -26,7 +26,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> { let config_rtcsel = rtc_config.clock_config as u8; #[cfg(not(any(rcc_wl5, rcc_wle)))] - let config_rtcsel = crate::pac::rcc::vals::Rtcsel(config_rtcsel); + let config_rtcsel = crate::pac::rcc::vals::Rtcsel::from_bits(config_rtcsel); if !reg.rtcen() || reg.rtcsel() != config_rtcsel { crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index 1cddac99..c3224073 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -650,7 +650,7 @@ fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> Br { _ => 0b111, }; - Br(val) + Br::from_bits(val) } trait RegsExt { @@ -772,7 +772,7 @@ fn set_rxdmaen(regs: Regs, val: bool) { fn finish_dma(regs: Regs) { #[cfg(spi_v2)] - while regs.sr().read().ftlvl() > 0 {} + while regs.sr().read().ftlvl().to_bits() > 0 {} #[cfg(any(spi_v3, spi_v4, spi_v5))] while !regs.sr().read().txc() {} diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 47a79c18..c97efbf0 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -869,7 +869,7 @@ fn configure(r: Regs, config: &Config, pclk_freq: Hertz, kind: Kind, enable_rx: _ => vals::Ps::EVEN, }); #[cfg(not(usart_v1))] - w.set_over8(vals::Over8(over8 as _)); + w.set_over8(vals::Over8::from_bits(over8 as _)); }); #[cfg(not(usart_v1))] diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs index 01b158b1..ecdd1d0b 100644 --- a/embassy-stm32/src/usb/usb.rs +++ b/embassy-stm32/src/usb/usb.rs @@ -97,8 +97,8 @@ impl interrupt::typelevel::Handler for InterruptHandl } epr.set_dtog_rx(false); epr.set_dtog_tx(false); - epr.set_stat_rx(Stat(0)); - epr.set_stat_tx(Stat(0)); + epr.set_stat_rx(Stat::from_bits(0)); + epr.set_stat_tx(Stat::from_bits(0)); epr.set_ctr_rx(!epr.ctr_rx()); epr.set_ctr_tx(!epr.ctr_tx()); regs.epr(index).write_value(epr); @@ -143,8 +143,8 @@ fn invariant(mut r: regs::Epr) -> regs::Epr { r.set_ctr_tx(true); // don't clear r.set_dtog_rx(false); // don't toggle r.set_dtog_tx(false); // don't toggle - r.set_stat_rx(Stat(0)); - r.set_stat_tx(Stat(0)); + r.set_stat_rx(Stat::from_bits(0)); + r.set_stat_tx(Stat::from_bits(0)); r } @@ -551,7 +551,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> { true => Stat::STALL, }; let mut w = invariant(r); - w.set_stat_tx(Stat(r.stat_tx().0 ^ want_stat.0)); + w.set_stat_tx(Stat::from_bits(r.stat_tx().to_bits() ^ want_stat.to_bits())); reg.write_value(w); } } @@ -570,7 +570,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> { true => Stat::STALL, }; let mut w = invariant(r); - w.set_stat_rx(Stat(r.stat_rx().0 ^ want_stat.0)); + w.set_stat_rx(Stat::from_bits(r.stat_rx().to_bits() ^ want_stat.to_bits())); reg.write_value(w); } } @@ -606,7 +606,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> { break; } let mut w = invariant(r); - w.set_stat_tx(Stat(r.stat_tx().0 ^ want_stat.0)); + w.set_stat_tx(Stat::from_bits(r.stat_tx().to_bits() ^ want_stat.to_bits())); reg.write_value(w); } EP_IN_WAKERS[ep_addr.index()].wake(); @@ -622,7 +622,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> { break; } let mut w = invariant(r); - w.set_stat_rx(Stat(r.stat_rx().0 ^ want_stat.0)); + w.set_stat_rx(Stat::from_bits(r.stat_rx().to_bits() ^ want_stat.to_bits())); reg.write_value(w); } EP_OUT_WAKERS[ep_addr.index()].wake(); @@ -763,8 +763,8 @@ impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> { regs.epr(index).write(|w| { w.set_ep_type(convert_type(self.info.ep_type)); w.set_ea(self.info.addr.index() as _); - w.set_stat_rx(Stat(Stat::NAK.0 ^ Stat::VALID.0)); - w.set_stat_tx(Stat(0)); + w.set_stat_rx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits())); + w.set_stat_tx(Stat::from_bits(0)); w.set_ctr_rx(true); // don't clear w.set_ctr_tx(true); // don't clear }); @@ -805,8 +805,8 @@ impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> { regs.epr(index).write(|w| { w.set_ep_type(convert_type(self.info.ep_type)); w.set_ea(self.info.addr.index() as _); - w.set_stat_tx(Stat(Stat::NAK.0 ^ Stat::VALID.0)); - w.set_stat_rx(Stat(0)); + w.set_stat_tx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits())); + w.set_stat_rx(Stat::from_bits(0)); w.set_ctr_rx(true); // don't clear w.set_ctr_tx(true); // don't clear }); @@ -869,19 +869,19 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { let mut stat_tx = 0; if first { // change NAK -> VALID - stat_rx ^= Stat::NAK.0 ^ Stat::VALID.0; - stat_tx ^= Stat::NAK.0 ^ Stat::STALL.0; + stat_rx ^= Stat::NAK.to_bits() ^ Stat::VALID.to_bits(); + stat_tx ^= Stat::NAK.to_bits() ^ Stat::STALL.to_bits(); } if last { // change STALL -> VALID - stat_tx ^= Stat::STALL.0 ^ Stat::NAK.0; + stat_tx ^= Stat::STALL.to_bits() ^ Stat::NAK.to_bits(); } // Note: if this is the first AND last transfer, the above effectively // changes stat_tx like NAK -> NAK, so noop. regs.epr(0).write(|w| { w.set_ep_type(EpType::CONTROL); - w.set_stat_rx(Stat(stat_rx)); - w.set_stat_tx(Stat(stat_tx)); + w.set_stat_rx(Stat::from_bits(stat_rx)); + w.set_stat_tx(Stat::from_bits(stat_tx)); w.set_ctr_rx(true); // don't clear w.set_ctr_tx(true); // don't clear }); @@ -908,11 +908,11 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { regs.epr(0).write(|w| { w.set_ep_type(EpType::CONTROL); - w.set_stat_rx(Stat(match last { + w.set_stat_rx(Stat::from_bits(match last { // If last, set STAT_RX=STALL. - true => Stat::NAK.0 ^ Stat::STALL.0, + true => Stat::NAK.to_bits() ^ Stat::STALL.to_bits(), // Otherwise, set STAT_RX=VALID, to allow the host to send the next packet. - false => Stat::NAK.0 ^ Stat::VALID.0, + false => Stat::NAK.to_bits() ^ Stat::VALID.to_bits(), })); w.set_ctr_rx(true); // don't clear w.set_ctr_tx(true); // don't clear @@ -937,17 +937,17 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { let mut stat_rx = 0; if first { // change NAK -> STALL - stat_rx ^= Stat::NAK.0 ^ Stat::STALL.0; + stat_rx ^= Stat::NAK.to_bits() ^ Stat::STALL.to_bits(); } if last { // change STALL -> VALID - stat_rx ^= Stat::STALL.0 ^ Stat::VALID.0; + stat_rx ^= Stat::STALL.to_bits() ^ Stat::VALID.to_bits(); } // Note: if this is the first AND last transfer, the above effectively // does a change of NAK -> VALID. regs.epr(0).write(|w| { w.set_ep_type(EpType::CONTROL); - w.set_stat_rx(Stat(stat_rx)); + w.set_stat_rx(Stat::from_bits(stat_rx)); w.set_ep_kind(last); // set OUT_STATUS if last. w.set_ctr_rx(true); // don't clear w.set_ctr_tx(true); // don't clear @@ -977,7 +977,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { let regs = T::regs(); regs.epr(0).write(|w| { w.set_ep_type(EpType::CONTROL); - w.set_stat_tx(Stat(Stat::NAK.0 ^ Stat::VALID.0)); + w.set_stat_tx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits())); w.set_ep_kind(last); // set OUT_STATUS if last. w.set_ctr_rx(true); // don't clear w.set_ctr_tx(true); // don't clear @@ -998,8 +998,8 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { let epr = regs.epr(0).read(); regs.epr(0).write(|w| { w.set_ep_type(EpType::CONTROL); - w.set_stat_rx(Stat(epr.stat_rx().0 ^ Stat::STALL.0)); - w.set_stat_tx(Stat(epr.stat_tx().0 ^ Stat::VALID.0)); + w.set_stat_rx(Stat::from_bits(epr.stat_rx().to_bits() ^ Stat::STALL.to_bits())); + w.set_stat_tx(Stat::from_bits(epr.stat_tx().to_bits() ^ Stat::VALID.to_bits())); w.set_ctr_rx(true); // don't clear w.set_ctr_tx(true); // don't clear }); @@ -1029,8 +1029,8 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { let epr = regs.epr(0).read(); regs.epr(0).write(|w| { w.set_ep_type(EpType::CONTROL); - w.set_stat_rx(Stat(epr.stat_rx().0 ^ Stat::STALL.0)); - w.set_stat_tx(Stat(epr.stat_tx().0 ^ Stat::STALL.0)); + w.set_stat_rx(Stat::from_bits(epr.stat_rx().to_bits() ^ Stat::STALL.to_bits())); + w.set_stat_tx(Stat::from_bits(epr.stat_tx().to_bits() ^ Stat::STALL.to_bits())); w.set_ctr_rx(true); // don't clear w.set_ctr_tx(true); // don't clear }); diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs index 6c00c93d..6783db28 100644 --- a/embassy-stm32/src/usb_otg/usb.rs +++ b/embassy-stm32/src/usb_otg/usb.rs @@ -97,7 +97,7 @@ impl interrupt::typelevel::Handler for InterruptHandl vals::Pktstsd::SETUP_DATA_DONE => { trace!("SETUP_DATA_DONE ep={}", ep_num); } - x => trace!("unknown PKTSTS: {}", x.0), + x => trace!("unknown PKTSTS: {}", x.to_bits()), } } @@ -920,7 +920,7 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> { trace!("enumdne"); let speed = r.dsts().read().enumspd(); - trace!(" speed={}", speed.0); + trace!(" speed={}", speed.to_bits()); r.gusbcfg().modify(|w| { w.set_trdt(calculate_trdt(speed, T::frequency())); diff --git a/embassy-stm32/src/wdg/mod.rs b/embassy-stm32/src/wdg/mod.rs index 5907a4e5..b03e81d6 100644 --- a/embassy-stm32/src/wdg/mod.rs +++ b/embassy-stm32/src/wdg/mod.rs @@ -49,7 +49,7 @@ impl<'d, T: Instance> IndependentWatchdog<'d, T> { let wdg = T::regs(); wdg.kr().write(|w| w.set_key(Key::ENABLE)); - wdg.pr().write(|w| w.set_pr(Pr(pr))); + wdg.pr().write(|w| w.set_pr(Pr::from_bits(pr))); wdg.rlr().write(|w| w.set_rl(rl)); trace!(