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stm32/rcc: port L4 to the "flattened" API like h5/h7.

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This commit is contained in:
Dario Nieuwenhuis
2023-10-15 03:08:14 +02:00
parent 7045c53170
commit 8a10948ce9
6 changed files with 275 additions and 194 deletions
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19
examples/stm32l4/src/bin/spe_adin1110_http_server.rs
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@ -48,7 +48,7 @@ use embassy_net_adin1110::{self, Device, Runner, ADIN1110};
use embedded_hal_bus::spi::ExclusiveDevice;
use hal::gpio::Pull;
use hal::i2c::Config as I2C_Config;
use hal::rcc::{ClockSrc, PLLSource, PllMul, PllPreDiv, PllRDiv};
use hal::rcc::{ClockSrc, PLLSource, Pll, PllMul, PllPreDiv, PllRDiv};
use hal::spi::{Config as SPI_Config, Spi};
use hal::time::Hertz;
@ -77,13 +77,16 @@ async fn main(spawner: Spawner) {
// 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2)
// 80MHz highest frequency for flash 0 wait.
config.rcc.mux = ClockSrc::PLL(
PLLSource::HSE(Hertz(8_000_000)),
PllRDiv::DIV2,
PllPreDiv::DIV1,
PllMul::MUL20,
None,
);
config.rcc.mux = ClockSrc::PLL;
config.rcc.hse = Some(Hertz::mhz(8));
config.rcc.pll_src = PLLSource::HSE;
config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL20,
divp: None,
divq: None,
divr: Some(PllRDiv::DIV2), // sysclk 80Mhz clock (8 / 1 * 20 / 2)
});
config.rcc.hsi48 = true; // needed for rng
let dp = embassy_stm32::init(config);