From e0ce7fcde7906fc219d294e858388e62ab107ec3 Mon Sep 17 00:00:00 2001 From: Scott Mabin Date: Sun, 30 Jul 2023 01:00:50 +0100 Subject: [PATCH] stm32f2 pll overflow with crystal With a large enough HSE input frequency, the vco clock calculation will overflow a u32. Therefore, in this specific case we have to use the inner value and cast to u64 to ensure the mul isn't clipped before applying the divider. --- embassy-stm32/src/rcc/f2.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/embassy-stm32/src/rcc/f2.rs b/embassy-stm32/src/rcc/f2.rs index 1525cc3c..bc240fcb 100644 --- a/embassy-stm32/src/rcc/f2.rs +++ b/embassy-stm32/src/rcc/f2.rs @@ -58,7 +58,7 @@ impl Default for PLLConfig { impl PLLConfig { pub fn clocks(&self, src_freq: Hertz) -> PLLClocks { let in_freq = src_freq / self.pre_div; - let vco_freq = src_freq * self.mul / self.pre_div; + let vco_freq = Hertz((src_freq.0 as u64 * self.mul.0 as u64 / self.pre_div.0 as u64) as u32); let main_freq = vco_freq / self.main_div; let pll48_freq = vco_freq / self.pll48_div; PLLClocks {