stm32/timer: Fix frequency off-by-one
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@ -46,7 +46,10 @@ pub(crate) mod sealed {
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assert!(f > 0);
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assert!(f > 0);
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let pclk_ticks_per_timer_period = timer_f / f;
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let pclk_ticks_per_timer_period = timer_f / f;
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let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 16)).try_into());
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let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 16)).try_into());
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let arr: u16 = unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into());
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let divide_by = pclk_ticks_per_timer_period / (u32::from(psc) + 1);
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// the timer counts `0..=arr`, we want it to count `0..divide_by`
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let arr = unwrap!(u16::try_from(divide_by - 1));
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let regs = Self::regs();
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let regs = Self::regs();
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regs.psc().write(|r| r.set_psc(psc));
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regs.psc().write(|r| r.set_psc(psc));
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