stm32: Refactor DMA interrupts
Previously, every dma interrupt handler called the same `on_irq` function which had to check the state of every dma channel. Now, each dma interrupt handler only calls an `on_irq` method for its corresponding channel or channels.
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@ -105,46 +105,37 @@ fn main() {
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// ========
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// ========
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// Generate DMA IRQs.
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// Generate DMA IRQs.
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let mut dma_irqs: HashSet<&str> = HashSet::new();
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let mut dma_irqs: HashMap<&str, Vec<(&str, &str)>> = HashMap::new();
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let mut bdma_irqs: HashSet<&str> = HashSet::new();
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for p in METADATA.peripherals {
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for p in METADATA.peripherals {
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if let Some(r) = &p.registers {
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if let Some(r) = &p.registers {
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match r.kind {
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if r.kind == "dma" || r.kind == "bdma" {
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"dma" => {
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for irq in p.interrupts {
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for irq in p.interrupts {
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dma_irqs.insert(irq.interrupt);
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dma_irqs
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.entry(irq.interrupt)
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.or_default()
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.push((p.name, irq.signal));
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}
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}
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}
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}
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"bdma" => {
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for irq in p.interrupts {
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bdma_irqs.insert(irq.interrupt);
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}
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}
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_ => {}
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}
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}
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}
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}
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}
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let tokens: Vec<_> = dma_irqs.iter().map(|s| format_ident!("{}", s)).collect();
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for (irq, channels) in dma_irqs {
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g.extend(quote! {
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let irq = format_ident!("{}", irq);
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#(
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#[crate::interrupt]
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let channels = channels
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unsafe fn #tokens () {
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.iter()
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crate::dma::dma::on_irq();
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.map(|(dma, ch)| format_ident!("{}_{}", dma, ch));
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}
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)*
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});
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let tokens: Vec<_> = bdma_irqs.iter().map(|s| format_ident!("{}", s)).collect();
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g.extend(quote! {
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g.extend(quote! {
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#(
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#[crate::interrupt]
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#[crate::interrupt]
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unsafe fn #tokens () {
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unsafe fn #irq () {
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crate::dma::bdma::on_irq();
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#(
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}
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<crate::peripherals::#channels as crate::dma::sealed::Channel>::on_irq();
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)*
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)*
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}
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});
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});
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}
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// ========
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// ========
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// Generate RccPeripheral impls
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// Generate RccPeripheral impls
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@ -38,26 +38,6 @@ impl State {
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static STATE: State = State::new();
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static STATE: State = State::new();
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pub(crate) unsafe fn on_irq() {
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foreach_peripheral! {
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(bdma, BDMA1) => {
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// BDMA1 in H7 doesn't use DMAMUX, which breaks
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};
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(bdma, $dma:ident) => {
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let isr = pac::$dma.isr().read();
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foreach_dma_channel! {
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($channel_peri:ident, $dma, bdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
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let cr = pac::$dma.ch($channel_num).cr();
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if isr.tcif($channel_num) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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STATE.ch_wakers[$index].wake();
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}
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};
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}
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};
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}
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}
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/// safety: must be called only once
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/// safety: must be called only once
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pub(crate) unsafe fn init() {
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pub(crate) unsafe fn init() {
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foreach_interrupt! {
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foreach_interrupt! {
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@ -150,6 +130,12 @@ foreach_dma_channel! {
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fn set_waker(&mut self, waker: &Waker) {
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fn set_waker(&mut self, waker: &Waker) {
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unsafe { low_level_api::set_waker($index, waker) }
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unsafe { low_level_api::set_waker($index, waker) }
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}
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}
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fn on_irq() {
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unsafe {
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low_level_api::on_irq_inner(pac::$dma_peri, $channel_num, $index);
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}
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}
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}
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}
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impl crate::dma::Channel for crate::peripherals::$channel_peri {}
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impl crate::dma::Channel for crate::peripherals::$channel_peri {}
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@ -243,4 +229,18 @@ mod low_level_api {
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w.set_teif(channel_number as _, true);
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w.set_teif(channel_number as _, true);
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});
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});
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}
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}
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/// Safety: Must be called with a matching set of parameters for a valid dma channel
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pub unsafe fn on_irq_inner(dma: pac::bdma::Dma, channel_num: u8, index: u8) {
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let channel_num = channel_num as usize;
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let index = index as usize;
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let isr = dma.isr().read();
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let cr = dma.ch(channel_num).cr();
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if isr.tcif(channel_num) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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STATE.ch_wakers[index].wake();
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}
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}
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}
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}
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@ -36,22 +36,6 @@ impl State {
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static STATE: State = State::new();
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static STATE: State = State::new();
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pub(crate) unsafe fn on_irq() {
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foreach_peripheral! {
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(dma, $dma:ident) => {
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foreach_dma_channel! {
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($channel_peri:ident, $dma, dma, $channel_num:expr, $index:expr, $dmamux:tt) => {
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let cr = pac::$dma.st($channel_num).cr();
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if pac::$dma.isr($channel_num/4).read().tcif($channel_num%4) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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STATE.ch_wakers[$index].wake();
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}
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};
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}
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};
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}
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}
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/// safety: must be called only once
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/// safety: must be called only once
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pub(crate) unsafe fn init() {
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pub(crate) unsafe fn init() {
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foreach_interrupt! {
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foreach_interrupt! {
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@ -137,6 +121,12 @@ foreach_dma_channel! {
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fn set_waker(&mut self, waker: &Waker) {
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fn set_waker(&mut self, waker: &Waker) {
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unsafe {low_level_api::set_waker($index, waker )}
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unsafe {low_level_api::set_waker($index, waker )}
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}
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}
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fn on_irq() {
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unsafe {
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low_level_api::on_irq_inner(pac::$dma_peri, $channel_num, $index);
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}
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}
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}
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}
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impl crate::dma::Channel for crate::peripherals::$channel_peri { }
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impl crate::dma::Channel for crate::peripherals::$channel_peri { }
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@ -240,4 +230,18 @@ mod low_level_api {
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w.set_teif(isrbit, true);
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w.set_teif(isrbit, true);
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});
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});
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}
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}
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/// Safety: Must be called with a matching set of parameters for a valid dma channel
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pub unsafe fn on_irq_inner(dma: pac::dma::Dma, channel_num: u8, index: u8) {
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let channel_num = channel_num as usize;
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let index = index as usize;
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let cr = dma.st(channel_num).cr();
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let isr = dma.isr(channel_num / 4).read();
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if isr.tcif(channel_num % 4) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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STATE.ch_wakers[index].wake();
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}
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}
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}
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}
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@ -88,6 +88,11 @@ pub(crate) mod sealed {
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/// Sets the waker that is called when this channel stops (either completed or manually stopped)
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/// Sets the waker that is called when this channel stops (either completed or manually stopped)
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fn set_waker(&mut self, waker: &Waker);
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fn set_waker(&mut self, waker: &Waker);
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/// This is called when this channel triggers an interrupt.
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/// Note: Because some channels share an interrupt, this function might be
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/// called for a channel that didn't trigger an interrupt.
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fn on_irq();
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}
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}
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}
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}
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