F0: usart + DMA working

embassy-stm32/src/bdma/v1.rs

@@ -78,7 +78,6 @@ pub(crate) async unsafe fn transfer_p2m(
     })
     .await;
 
-    on_drop.defuse();
     // TODO handle error
     assert!(res == CH_STATUS_COMPLETED);
 }
@@ -128,7 +127,6 @@ pub(crate) async unsafe fn transfer_m2p(
     })
     .await;
 
-    on_drop.defuse();
     // TODO handle error
     assert!(res == CH_STATUS_COMPLETED);
 }
@@ -150,7 +148,6 @@ unsafe fn on_irq() {
                         STATE.ch_wakers[n].wake();
                     }
                 }
-
         };
     }
 }
@@ -162,6 +159,13 @@ pub(crate) unsafe fn init() {
             crate::interrupt::$irq::steal().enable();
         };
     }
+    pac::peripherals! {
+        (bdma, DMA1) => {
+            critical_section::with(|_| {
+                pac::RCC.ahbenr().modify(|w| w.set_dmaen(true));
+            });
+        };
+    }
 }
 
 pub(crate) mod sealed {
@@ -285,3 +289,17 @@ pac::interrupts! {
         }
     };
 }
+
+#[cfg(usart)]
+use crate::usart;
+pac::peripheral_dma_channels! {
+    ($peri:ident, usart, $kind:ident, RX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
+        impl usart::RxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
+        impl usart::sealed::RxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
+    };
+
+    ($peri:ident, usart, $kind:ident, TX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
+        impl usart::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
+        impl usart::sealed::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
+    };
+}

embassy-stm32/src/usart/mod.rs

@@ -8,7 +8,6 @@ use crate::peripherals;
 pub use _version::*;
 
 use crate::gpio::Pin;
-use crate::pac::usart::Usart;
 use crate::rcc::RccPeripheral;
 
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
@@ -58,6 +57,7 @@ impl Default for Config {
 
 /// Serial error
 #[derive(Debug, Eq, PartialEq, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[non_exhaustive]
 pub enum Error {
     /// Framing error
@@ -76,8 +76,11 @@ pub(crate) mod sealed {
     #[cfg(any(dma, dmamux))]
     use crate::dma::WriteDma;
 
+    #[cfg(bdma)]
+    use crate::bdma::WriteDma;
+
     pub trait Instance {
-        fn regs(&self) -> Usart;
+        fn regs(&self) -> crate::pac::usart::Usart;
     }
     pub trait RxPin<T: Instance>: Pin {
         fn af_num(&self) -> u8;
@@ -95,10 +98,10 @@ pub(crate) mod sealed {
         fn af_num(&self) -> u8;
     }
 
-    #[cfg(any(dma, dmamux))]
+    #[cfg(any(bdma, dma, dmamux))]
     pub trait RxDma<T: Instance> {}
 
-    #[cfg(any(dma, dmamux))]
+    #[cfg(any(bdma, dma, dmamux))]
     pub trait TxDma<T: Instance>: WriteDma<T> {}
 }
 
@@ -109,10 +112,10 @@ pub trait CtsPin<T: Instance>: sealed::CtsPin<T> {}
 pub trait RtsPin<T: Instance>: sealed::RtsPin<T> {}
 pub trait CkPin<T: Instance>: sealed::CkPin<T> {}
 
-#[cfg(any(dma, dmamux))]
+#[cfg(any(bdma, dma, dmamux))]
 pub trait RxDma<T: Instance>: sealed::RxDma<T> {}
 
-#[cfg(any(dma, dmamux))]
+#[cfg(any(bdma, dma, dmamux))]
 pub trait TxDma<T: Instance>: sealed::TxDma<T> {}
 
 crate::pac::peripherals!(

embassy-stm32/src/usart/v2.rs

@@ -3,7 +3,7 @@ use core::marker::PhantomData;
 use embassy::util::Unborrow;
 use embassy_extras::unborrow;
 
-use crate::pac::usart::{regs, vals};
+use crate::pac::usart::vals;
 
 use super::*;
 
@@ -21,7 +21,6 @@ impl<'d, T: Instance> Uart<'d, T> {
     ) -> Self {
         unborrow!(inner, rx, tx);
 
-        // Uncomment once we find all of the H7's UART clocks.
         T::enable();
         let pclk_freq = T::frequency();
 
@@ -34,7 +33,10 @@ impl<'d, T: Instance> Uart<'d, T> {
             rx.set_as_af(rx.af_num());
             tx.set_as_af(tx.af_num());
 
-            r.brr().write_value(regs::Brr(div));
+            r.cr2().write(|_w| {});
+            r.cr3().write(|_w| {});
+
+            r.brr().write(|w| w.set_brr(div as u16));
             r.cr1().write(|w| {
                 w.set_ue(true);
                 w.set_te(true);
@@ -48,8 +50,6 @@ impl<'d, T: Instance> Uart<'d, T> {
                     _ => vals::Ps::EVEN,
                 });
             });
-            r.cr2().write(|_w| {});
-            r.cr3().write(|_w| {});
         }
 
         Self {
@@ -58,7 +58,7 @@ impl<'d, T: Instance> Uart<'d, T> {
         }
     }
 
-    #[cfg(dma)]
+    #[cfg(bdma)]
     pub async fn write_dma(&mut self, ch: &mut impl TxDma<T>, buffer: &[u8]) -> Result<(), Error> {
         unsafe {
             self.inner.regs().cr3().modify(|reg| {