stm32/i2c: remove _timeout public API, share more code between v1/v2.
This commit is contained in:
Dario Nieuwenhuis
parent
42f5c8109b
commit
91e107ea07
@ -1,17 +1,23 @@
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#![macro_use]
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use core::marker::PhantomData;
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use crate::dma::NoDma;
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use crate::interrupt;
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#[cfg_attr(i2c_v1, path = "v1.rs")]
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#[cfg_attr(i2c_v2, path = "v2.rs")]
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mod _version;
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pub use _version::*;
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use embassy_sync::waitqueue::AtomicWaker;
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use crate::peripherals;
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use core::future::Future;
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use core::marker::PhantomData;
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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#[cfg(feature = "time")]
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use embassy_time::{Duration, Instant};
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use crate::dma::NoDma;
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use crate::gpio::sealed::AFType;
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use crate::gpio::Pull;
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use crate::interrupt::typelevel::Interrupt;
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use crate::time::Hertz;
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use crate::{interrupt, peripherals};
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/// I2C error.
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#[derive(Debug, PartialEq, Eq)]
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@ -33,6 +39,148 @@ pub enum Error {
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ZeroLengthTransfer,
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}
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/// I2C config
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#[non_exhaustive]
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#[derive(Copy, Clone)]
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pub struct Config {
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/// Enable internal pullup on SDA.
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///
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/// Using external pullup resistors is recommended for I2C. If you do
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/// have external pullups you should not enable this.
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pub sda_pullup: bool,
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/// Enable internal pullup on SCL.
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///
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/// Using external pullup resistors is recommended for I2C. If you do
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/// have external pullups you should not enable this.
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pub scl_pullup: bool,
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/// Timeout.
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#[cfg(feature = "time")]
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pub timeout: embassy_time::Duration,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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sda_pullup: false,
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scl_pullup: false,
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#[cfg(feature = "time")]
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timeout: embassy_time::Duration::from_millis(1000),
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}
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}
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}
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/// I2C driver.
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pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
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_peri: PeripheralRef<'d, T>,
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#[allow(dead_code)]
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tx_dma: PeripheralRef<'d, TXDMA>,
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#[allow(dead_code)]
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rx_dma: PeripheralRef<'d, RXDMA>,
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#[cfg(feature = "time")]
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timeout: Duration,
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}
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impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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/// Create a new I2C driver.
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
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+ interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
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+ 'd,
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tx_dma: impl Peripheral<P = TXDMA> + 'd,
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rx_dma: impl Peripheral<P = RXDMA> + 'd,
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(peri, scl, sda, tx_dma, rx_dma);
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T::enable_and_reset();
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scl.set_as_af_pull(
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scl.af_num(),
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AFType::OutputOpenDrain,
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match config.scl_pullup {
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true => Pull::Up,
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false => Pull::None,
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},
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);
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sda.set_as_af_pull(
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sda.af_num(),
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AFType::OutputOpenDrain,
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match config.sda_pullup {
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true => Pull::Up,
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false => Pull::None,
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},
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);
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unsafe { T::EventInterrupt::enable() };
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unsafe { T::ErrorInterrupt::enable() };
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let mut this = Self {
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_peri: peri,
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tx_dma,
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rx_dma,
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#[cfg(feature = "time")]
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timeout: config.timeout,
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};
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this.init(freq, config);
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this
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}
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fn timeout(&self) -> Timeout {
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Timeout {
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#[cfg(feature = "time")]
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deadline: Instant::now() + self.timeout,
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}
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}
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}
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#[derive(Copy, Clone)]
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struct Timeout {
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#[cfg(feature = "time")]
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deadline: Instant,
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}
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#[allow(dead_code)]
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impl Timeout {
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#[cfg(not(feature = "time"))]
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#[inline]
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fn check(self) -> Result<(), Error> {
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Ok(())
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}
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#[cfg(feature = "time")]
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#[inline]
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fn check(self) -> Result<(), Error> {
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if Instant::now() > self.deadline {
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Err(Error::Timeout)
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} else {
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Ok(())
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}
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}
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#[cfg(not(feature = "time"))]
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#[inline]
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fn with<R>(self, fut: impl Future<Output = Result<R, Error>>) -> impl Future<Output = Result<R, Error>> {
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fut
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}
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#[cfg(feature = "time")]
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#[inline]
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fn with<R>(self, fut: impl Future<Output = Result<R, Error>>) -> impl Future<Output = Result<R, Error>> {
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use futures::FutureExt;
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embassy_futures::select::select(embassy_time::Timer::at(self.deadline), fut).map(|r| match r {
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embassy_futures::select::Either::First(_) => Err(Error::Timeout),
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embassy_futures::select::Either::Second(r) => r,
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})
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}
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}
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pub(crate) mod sealed {
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use super::*;
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@ -1,20 +1,14 @@
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::task::Poll;
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use embassy_embedded_hal::SetConfig;
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use embassy_futures::select::{select, Either};
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use embassy_hal_internal::drop::OnDrop;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use super::*;
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use crate::dma::{NoDma, Transfer};
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use crate::gpio::sealed::AFType;
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use crate::gpio::Pull;
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use crate::interrupt::typelevel::Interrupt;
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use crate::dma::Transfer;
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use crate::pac::i2c;
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use crate::time::Hertz;
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use crate::{interrupt, Peripheral};
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pub unsafe fn on_interrupt<T: Instance>() {
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let regs = T::regs();
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@ -30,55 +24,8 @@ pub unsafe fn on_interrupt<T: Instance>() {
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});
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}
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#[non_exhaustive]
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#[derive(Copy, Clone, Default)]
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pub struct Config {
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pub sda_pullup: bool,
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pub scl_pullup: bool,
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}
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pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
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phantom: PhantomData<&'d mut T>,
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#[allow(dead_code)]
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tx_dma: PeripheralRef<'d, TXDMA>,
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#[allow(dead_code)]
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rx_dma: PeripheralRef<'d, RXDMA>,
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}
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impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
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+ interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
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+ 'd,
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tx_dma: impl Peripheral<P = TXDMA> + 'd,
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rx_dma: impl Peripheral<P = RXDMA> + 'd,
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(scl, sda, tx_dma, rx_dma);
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T::enable_and_reset();
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scl.set_as_af_pull(
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scl.af_num(),
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AFType::OutputOpenDrain,
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match config.scl_pullup {
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true => Pull::Up,
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false => Pull::None,
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},
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);
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sda.set_as_af_pull(
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sda.af_num(),
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AFType::OutputOpenDrain,
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match config.sda_pullup {
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true => Pull::Up,
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false => Pull::None,
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},
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);
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pub(crate) fn init(&mut self, freq: Hertz, _config: Config) {
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T::regs().cr1().modify(|reg| {
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reg.set_pe(false);
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//reg.set_anfoff(false);
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@ -101,15 +48,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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T::regs().cr1().modify(|reg| {
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reg.set_pe(true);
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});
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unsafe { T::EventInterrupt::enable() };
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unsafe { T::ErrorInterrupt::enable() };
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Self {
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phantom: PhantomData,
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tx_dma,
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rx_dma,
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}
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}
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fn check_and_clear_error_flags() -> Result<i2c::regs::Sr1, Error> {
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@ -169,12 +107,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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Ok(sr1)
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}
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fn write_bytes(
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&mut self,
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addr: u8,
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bytes: &[u8],
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check_timeout: impl Fn() -> Result<(), Error>,
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) -> Result<(), Error> {
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fn write_bytes(&mut self, addr: u8, bytes: &[u8], timeout: Timeout) -> Result<(), Error> {
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// Send a START condition
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T::regs().cr1().modify(|reg| {
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@ -183,7 +116,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Wait until START condition was generated
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while !Self::check_and_clear_error_flags()?.start() {
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check_timeout()?;
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timeout.check()?;
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}
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// Also wait until signalled we're master and everything is waiting for us
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@ -193,7 +126,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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let sr2 = T::regs().sr2().read();
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!sr2.msl() && !sr2.busy()
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} {
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check_timeout()?;
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timeout.check()?;
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}
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// Set up current address, we're trying to talk to
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@ -203,7 +136,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Wait for the address to be acknowledged
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// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
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while !Self::check_and_clear_error_flags()?.addr() {
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check_timeout()?;
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timeout.check()?;
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}
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// Clear condition by reading SR2
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@ -211,20 +144,20 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Send bytes
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for c in bytes {
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self.send_byte(*c, &check_timeout)?;
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self.send_byte(*c, timeout)?;
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}
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// Fallthrough is success
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Ok(())
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}
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fn send_byte(&self, byte: u8, check_timeout: impl Fn() -> Result<(), Error>) -> Result<(), Error> {
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fn send_byte(&self, byte: u8, timeout: Timeout) -> Result<(), Error> {
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// Wait until we're ready for sending
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while {
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// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
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!Self::check_and_clear_error_flags()?.txe()
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} {
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check_timeout()?;
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timeout.check()?;
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}
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// Push out a byte of data
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@ -235,32 +168,27 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Check for any potential error conditions.
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!Self::check_and_clear_error_flags()?.btf()
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} {
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check_timeout()?;
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timeout.check()?;
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}
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Ok(())
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}
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fn recv_byte(&self, check_timeout: impl Fn() -> Result<(), Error>) -> Result<u8, Error> {
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fn recv_byte(&self, timeout: Timeout) -> Result<u8, Error> {
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while {
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// Check for any potential error conditions.
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Self::check_and_clear_error_flags()?;
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!T::regs().sr1().read().rxne()
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} {
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check_timeout()?;
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timeout.check()?;
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}
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let value = T::regs().dr().read().dr();
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Ok(value)
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}
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pub fn blocking_read_timeout(
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&mut self,
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addr: u8,
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buffer: &mut [u8],
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check_timeout: impl Fn() -> Result<(), Error>,
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) -> Result<(), Error> {
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fn blocking_read_timeout(&mut self, addr: u8, buffer: &mut [u8], timeout: Timeout) -> Result<(), Error> {
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if let Some((last, buffer)) = buffer.split_last_mut() {
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// Send a START condition and set ACK bit
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T::regs().cr1().modify(|reg| {
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@ -270,7 +198,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Wait until START condition was generated
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while !Self::check_and_clear_error_flags()?.start() {
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check_timeout()?;
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timeout.check()?;
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}
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// Also wait until signalled we're master and everything is waiting for us
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@ -278,7 +206,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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let sr2 = T::regs().sr2().read();
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!sr2.msl() && !sr2.busy()
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} {
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check_timeout()?;
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timeout.check()?;
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}
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// Set up current address, we're trying to talk to
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@ -287,7 +215,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Wait until address was sent
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// Wait for the address to be acknowledged
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while !Self::check_and_clear_error_flags()?.addr() {
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check_timeout()?;
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timeout.check()?;
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}
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// Clear condition by reading SR2
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@ -295,7 +223,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Receive bytes into buffer
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for c in buffer {
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*c = self.recv_byte(&check_timeout)?;
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*c = self.recv_byte(timeout)?;
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}
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// Prepare to send NACK then STOP after next byte
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@ -305,11 +233,11 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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});
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// Receive last byte
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*last = self.recv_byte(&check_timeout)?;
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*last = self.recv_byte(timeout)?;
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// Wait for the STOP to be sent.
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while T::regs().cr1().read().stop() {
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check_timeout()?;
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timeout.check()?;
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}
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// Fallthrough is success
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@ -320,48 +248,33 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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}
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pub fn blocking_read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Error> {
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self.blocking_read_timeout(addr, read, || Ok(()))
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self.blocking_read_timeout(addr, read, self.timeout())
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}
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pub fn blocking_write_timeout(
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&mut self,
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addr: u8,
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write: &[u8],
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check_timeout: impl Fn() -> Result<(), Error>,
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) -> Result<(), Error> {
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self.write_bytes(addr, write, &check_timeout)?;
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pub fn blocking_write(&mut self, addr: u8, write: &[u8]) -> Result<(), Error> {
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let timeout = self.timeout();
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self.write_bytes(addr, write, timeout)?;
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// Send a STOP condition
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T::regs().cr1().modify(|reg| reg.set_stop(true));
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// Wait for STOP condition to transmit.
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while T::regs().cr1().read().stop() {
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check_timeout()?;
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timeout.check()?;
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}
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// Fallthrough is success
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Ok(())
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}
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pub fn blocking_write(&mut self, addr: u8, write: &[u8]) -> Result<(), Error> {
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self.blocking_write_timeout(addr, write, || Ok(()))
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}
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pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
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let timeout = self.timeout();
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pub fn blocking_write_read_timeout(
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&mut self,
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addr: u8,
|
||||
write: &[u8],
|
||||
read: &mut [u8],
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
self.write_bytes(addr, write, &check_timeout)?;
|
||||
self.blocking_read_timeout(addr, read, &check_timeout)?;
|
||||
self.write_bytes(addr, write, timeout)?;
|
||||
self.blocking_read_timeout(addr, read, timeout)?;
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
|
||||
self.blocking_write_read_timeout(addr, write, read, || Ok(()))
|
||||
}
|
||||
|
||||
// Async
|
||||
|
||||
#[inline] // pretty sure this should always be inlined
|
||||
|
||||
@ -4,37 +4,13 @@ use core::task::Poll;
|
||||
|
||||
use embassy_embedded_hal::SetConfig;
|
||||
use embassy_hal_internal::drop::OnDrop;
|
||||
use embassy_hal_internal::{into_ref, PeripheralRef};
|
||||
#[cfg(feature = "time")]
|
||||
use embassy_time::{Duration, Instant};
|
||||
|
||||
use super::*;
|
||||
use crate::dma::{NoDma, Transfer};
|
||||
use crate::gpio::sealed::AFType;
|
||||
use crate::gpio::Pull;
|
||||
use crate::interrupt::typelevel::Interrupt;
|
||||
use crate::dma::Transfer;
|
||||
use crate::pac::i2c;
|
||||
use crate::time::Hertz;
|
||||
use crate::{interrupt, Peripheral};
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
fn timeout_fn(timeout: Duration) -> impl Fn() -> Result<(), Error> {
|
||||
let deadline = Instant::now() + timeout;
|
||||
move || {
|
||||
if Instant::now() > deadline {
|
||||
Err(Error::Timeout)
|
||||
} else {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn no_timeout_fn() -> impl Fn() -> Result<(), Error> {
|
||||
move || Ok(())
|
||||
}
|
||||
|
||||
pub unsafe fn on_interrupt<T: Instance>() {
|
||||
pub(crate) unsafe fn on_interrupt<T: Instance>() {
|
||||
let regs = T::regs();
|
||||
let isr = regs.isr().read();
|
||||
|
||||
@ -48,70 +24,8 @@ pub unsafe fn on_interrupt<T: Instance>() {
|
||||
});
|
||||
}
|
||||
|
||||
#[non_exhaustive]
|
||||
#[derive(Copy, Clone)]
|
||||
pub struct Config {
|
||||
pub sda_pullup: bool,
|
||||
pub scl_pullup: bool,
|
||||
#[cfg(feature = "time")]
|
||||
pub transaction_timeout: Duration,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
sda_pullup: false,
|
||||
scl_pullup: false,
|
||||
#[cfg(feature = "time")]
|
||||
transaction_timeout: Duration::from_millis(100),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
|
||||
_peri: PeripheralRef<'d, T>,
|
||||
#[allow(dead_code)]
|
||||
tx_dma: PeripheralRef<'d, TXDMA>,
|
||||
#[allow(dead_code)]
|
||||
rx_dma: PeripheralRef<'d, RXDMA>,
|
||||
#[cfg(feature = "time")]
|
||||
timeout: Duration,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
pub fn new(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
scl: impl Peripheral<P = impl SclPin<T>> + 'd,
|
||||
sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
|
||||
_irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
|
||||
+ interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
|
||||
+ 'd,
|
||||
tx_dma: impl Peripheral<P = TXDMA> + 'd,
|
||||
rx_dma: impl Peripheral<P = RXDMA> + 'd,
|
||||
freq: Hertz,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, scl, sda, tx_dma, rx_dma);
|
||||
|
||||
T::enable_and_reset();
|
||||
|
||||
scl.set_as_af_pull(
|
||||
scl.af_num(),
|
||||
AFType::OutputOpenDrain,
|
||||
match config.scl_pullup {
|
||||
true => Pull::Up,
|
||||
false => Pull::None,
|
||||
},
|
||||
);
|
||||
sda.set_as_af_pull(
|
||||
sda.af_num(),
|
||||
AFType::OutputOpenDrain,
|
||||
match config.sda_pullup {
|
||||
true => Pull::Up,
|
||||
false => Pull::None,
|
||||
},
|
||||
);
|
||||
|
||||
pub(crate) fn init(&mut self, freq: Hertz, _config: Config) {
|
||||
T::regs().cr1().modify(|reg| {
|
||||
reg.set_pe(false);
|
||||
reg.set_anfoff(false);
|
||||
@ -130,17 +44,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
T::regs().cr1().modify(|reg| {
|
||||
reg.set_pe(true);
|
||||
});
|
||||
|
||||
unsafe { T::EventInterrupt::enable() };
|
||||
unsafe { T::ErrorInterrupt::enable() };
|
||||
|
||||
Self {
|
||||
_peri: peri,
|
||||
tx_dma,
|
||||
rx_dma,
|
||||
#[cfg(feature = "time")]
|
||||
timeout: config.transaction_timeout,
|
||||
}
|
||||
}
|
||||
|
||||
fn master_stop(&mut self) {
|
||||
@ -153,7 +56,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
stop: Stop,
|
||||
reload: bool,
|
||||
restart: bool,
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
timeout: Timeout,
|
||||
) -> Result<(), Error> {
|
||||
assert!(length < 256);
|
||||
|
||||
@ -162,7 +65,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
// automatically. This could be up to 50% of a bus
|
||||
// cycle (ie. up to 0.5/freq)
|
||||
while T::regs().cr2().read().start() {
|
||||
check_timeout()?;
|
||||
timeout.check()?;
|
||||
}
|
||||
}
|
||||
|
||||
@ -189,20 +92,14 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn master_write(
|
||||
address: u8,
|
||||
length: usize,
|
||||
stop: Stop,
|
||||
reload: bool,
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
fn master_write(address: u8, length: usize, stop: Stop, reload: bool, timeout: Timeout) -> Result<(), Error> {
|
||||
assert!(length < 256);
|
||||
|
||||
// Wait for any previous address sequence to end
|
||||
// automatically. This could be up to 50% of a bus
|
||||
// cycle (ie. up to 0.5/freq)
|
||||
while T::regs().cr2().read().start() {
|
||||
check_timeout()?;
|
||||
timeout.check()?;
|
||||
}
|
||||
|
||||
let reload = if reload {
|
||||
@ -227,15 +124,11 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn master_continue(
|
||||
length: usize,
|
||||
reload: bool,
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
fn master_continue(length: usize, reload: bool, timeout: Timeout) -> Result<(), Error> {
|
||||
assert!(length < 256 && length > 0);
|
||||
|
||||
while !T::regs().isr().read().tcr() {
|
||||
check_timeout()?;
|
||||
timeout.check()?;
|
||||
}
|
||||
|
||||
let reload = if reload {
|
||||
@ -261,7 +154,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
}
|
||||
}
|
||||
|
||||
fn wait_txe(&self, check_timeout: impl Fn() -> Result<(), Error>) -> Result<(), Error> {
|
||||
fn wait_txe(&self, timeout: Timeout) -> Result<(), Error> {
|
||||
loop {
|
||||
let isr = T::regs().isr().read();
|
||||
if isr.txe() {
|
||||
@ -278,11 +171,11 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
return Err(Error::Nack);
|
||||
}
|
||||
|
||||
check_timeout()?;
|
||||
timeout.check()?;
|
||||
}
|
||||
}
|
||||
|
||||
fn wait_rxne(&self, check_timeout: impl Fn() -> Result<(), Error>) -> Result<(), Error> {
|
||||
fn wait_rxne(&self, timeout: Timeout) -> Result<(), Error> {
|
||||
loop {
|
||||
let isr = T::regs().isr().read();
|
||||
if isr.rxne() {
|
||||
@ -299,11 +192,11 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
return Err(Error::Nack);
|
||||
}
|
||||
|
||||
check_timeout()?;
|
||||
timeout.check()?;
|
||||
}
|
||||
}
|
||||
|
||||
fn wait_tc(&self, check_timeout: impl Fn() -> Result<(), Error>) -> Result<(), Error> {
|
||||
fn wait_tc(&self, timeout: Timeout) -> Result<(), Error> {
|
||||
loop {
|
||||
let isr = T::regs().isr().read();
|
||||
if isr.tc() {
|
||||
@ -320,17 +213,11 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
return Err(Error::Nack);
|
||||
}
|
||||
|
||||
check_timeout()?;
|
||||
timeout.check()?;
|
||||
}
|
||||
}
|
||||
|
||||
fn read_internal(
|
||||
&mut self,
|
||||
address: u8,
|
||||
read: &mut [u8],
|
||||
restart: bool,
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
fn read_internal(&mut self, address: u8, read: &mut [u8], restart: bool, timeout: Timeout) -> Result<(), Error> {
|
||||
let completed_chunks = read.len() / 255;
|
||||
let total_chunks = if completed_chunks * 255 == read.len() {
|
||||
completed_chunks
|
||||
@ -345,17 +232,17 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
Stop::Automatic,
|
||||
last_chunk_idx != 0,
|
||||
restart,
|
||||
&check_timeout,
|
||||
timeout,
|
||||
)?;
|
||||
|
||||
for (number, chunk) in read.chunks_mut(255).enumerate() {
|
||||
if number != 0 {
|
||||
Self::master_continue(chunk.len(), number != last_chunk_idx, &check_timeout)?;
|
||||
Self::master_continue(chunk.len(), number != last_chunk_idx, timeout)?;
|
||||
}
|
||||
|
||||
for byte in chunk {
|
||||
// Wait until we have received something
|
||||
self.wait_rxne(&check_timeout)?;
|
||||
self.wait_rxne(timeout)?;
|
||||
|
||||
*byte = T::regs().rxdr().read().rxdata();
|
||||
}
|
||||
@ -363,13 +250,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn write_internal(
|
||||
&mut self,
|
||||
address: u8,
|
||||
write: &[u8],
|
||||
send_stop: bool,
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
fn write_internal(&mut self, address: u8, write: &[u8], send_stop: bool, timeout: Timeout) -> Result<(), Error> {
|
||||
let completed_chunks = write.len() / 255;
|
||||
let total_chunks = if completed_chunks * 255 == write.len() {
|
||||
completed_chunks
|
||||
@ -386,7 +267,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
write.len().min(255),
|
||||
Stop::Software,
|
||||
last_chunk_idx != 0,
|
||||
&check_timeout,
|
||||
timeout,
|
||||
) {
|
||||
if send_stop {
|
||||
self.master_stop();
|
||||
@ -396,14 +277,14 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
|
||||
for (number, chunk) in write.chunks(255).enumerate() {
|
||||
if number != 0 {
|
||||
Self::master_continue(chunk.len(), number != last_chunk_idx, &check_timeout)?;
|
||||
Self::master_continue(chunk.len(), number != last_chunk_idx, timeout)?;
|
||||
}
|
||||
|
||||
for byte in chunk {
|
||||
// Wait until we are allowed to send data
|
||||
// (START has been ACKed or last byte when
|
||||
// through)
|
||||
if let Err(err) = self.wait_txe(&check_timeout) {
|
||||
if let Err(err) = self.wait_txe(timeout) {
|
||||
if send_stop {
|
||||
self.master_stop();
|
||||
}
|
||||
@ -414,7 +295,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
}
|
||||
}
|
||||
// Wait until the write finishes
|
||||
let result = self.wait_tc(&check_timeout);
|
||||
let result = self.wait_tc(timeout);
|
||||
if send_stop {
|
||||
self.master_stop();
|
||||
}
|
||||
@ -427,7 +308,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
write: &[u8],
|
||||
first_slice: bool,
|
||||
last_slice: bool,
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
timeout: Timeout,
|
||||
) -> Result<(), Error>
|
||||
where
|
||||
TXDMA: crate::i2c::TxDma<T>,
|
||||
@ -473,10 +354,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
total_len.min(255),
|
||||
Stop::Software,
|
||||
(total_len > 255) || !last_slice,
|
||||
&check_timeout,
|
||||
timeout,
|
||||
)?;
|
||||
} else {
|
||||
Self::master_continue(total_len.min(255), (total_len > 255) || !last_slice, &check_timeout)?;
|
||||
Self::master_continue(total_len.min(255), (total_len > 255) || !last_slice, timeout)?;
|
||||
T::regs().cr1().modify(|w| w.set_tcie(true));
|
||||
}
|
||||
} else if !(isr.tcr() || isr.tc()) {
|
||||
@ -487,7 +368,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
} else {
|
||||
let last_piece = (remaining_len <= 255) && last_slice;
|
||||
|
||||
if let Err(e) = Self::master_continue(remaining_len.min(255), !last_piece, &check_timeout) {
|
||||
if let Err(e) = Self::master_continue(remaining_len.min(255), !last_piece, timeout) {
|
||||
return Poll::Ready(Err(e));
|
||||
}
|
||||
T::regs().cr1().modify(|w| w.set_tcie(true));
|
||||
@ -502,7 +383,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
|
||||
if last_slice {
|
||||
// This should be done already
|
||||
self.wait_tc(&check_timeout)?;
|
||||
self.wait_tc(timeout)?;
|
||||
self.master_stop();
|
||||
}
|
||||
|
||||
@ -516,7 +397,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
address: u8,
|
||||
buffer: &mut [u8],
|
||||
restart: bool,
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
timeout: Timeout,
|
||||
) -> Result<(), Error>
|
||||
where
|
||||
RXDMA: crate::i2c::RxDma<T>,
|
||||
@ -558,7 +439,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
Stop::Software,
|
||||
total_len > 255,
|
||||
restart,
|
||||
&check_timeout,
|
||||
timeout,
|
||||
)?;
|
||||
} else if !(isr.tcr() || isr.tc()) {
|
||||
// poll_fn was woken without an interrupt present
|
||||
@ -568,7 +449,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
} else {
|
||||
let last_piece = remaining_len <= 255;
|
||||
|
||||
if let Err(e) = Self::master_continue(remaining_len.min(255), !last_piece, &check_timeout) {
|
||||
if let Err(e) = Self::master_continue(remaining_len.min(255), !last_piece, timeout) {
|
||||
return Poll::Ready(Err(e));
|
||||
}
|
||||
T::regs().cr1().modify(|w| w.set_tcie(true));
|
||||
@ -582,7 +463,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
dma_transfer.await;
|
||||
|
||||
// This should be done already
|
||||
self.wait_tc(&check_timeout)?;
|
||||
self.wait_tc(timeout)?;
|
||||
self.master_stop();
|
||||
|
||||
drop(on_drop);
|
||||
@ -592,41 +473,31 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
|
||||
// =========================
|
||||
// Async public API
|
||||
#[cfg(feature = "time")]
|
||||
|
||||
/// Write.
|
||||
pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
|
||||
where
|
||||
TXDMA: crate::i2c::TxDma<T>,
|
||||
{
|
||||
let timeout = self.timeout();
|
||||
if write.is_empty() {
|
||||
self.write_internal(address, write, true, timeout_fn(self.timeout))
|
||||
self.write_internal(address, write, true, timeout)
|
||||
} else {
|
||||
embassy_time::with_timeout(
|
||||
self.timeout,
|
||||
self.write_dma_internal(address, write, true, true, timeout_fn(self.timeout)),
|
||||
)
|
||||
.await
|
||||
.unwrap_or(Err(Error::Timeout))
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
|
||||
where
|
||||
TXDMA: crate::i2c::TxDma<T>,
|
||||
{
|
||||
if write.is_empty() {
|
||||
self.write_internal(address, write, true, no_timeout_fn())
|
||||
} else {
|
||||
self.write_dma_internal(address, write, true, true, no_timeout_fn())
|
||||
timeout
|
||||
.with(self.write_dma_internal(address, write, true, true, timeout))
|
||||
.await
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
/// Write multiple buffers.
|
||||
///
|
||||
/// The buffers are concatenated in a single write transaction.
|
||||
pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error>
|
||||
where
|
||||
TXDMA: crate::i2c::TxDma<T>,
|
||||
{
|
||||
let timeout = self.timeout();
|
||||
|
||||
if write.is_empty() {
|
||||
return Err(Error::ZeroLengthTransfer);
|
||||
}
|
||||
@ -638,123 +509,49 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
let next = iter.next();
|
||||
let is_last = next.is_none();
|
||||
|
||||
embassy_time::with_timeout(
|
||||
self.timeout,
|
||||
self.write_dma_internal(address, c, first, is_last, timeout_fn(self.timeout)),
|
||||
)
|
||||
.await
|
||||
.unwrap_or(Err(Error::Timeout))?;
|
||||
let fut = self.write_dma_internal(address, c, first, is_last, timeout);
|
||||
timeout.with(fut).await?;
|
||||
first = false;
|
||||
current = next;
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error>
|
||||
where
|
||||
TXDMA: crate::i2c::TxDma<T>,
|
||||
{
|
||||
if write.is_empty() {
|
||||
return Err(Error::ZeroLengthTransfer);
|
||||
}
|
||||
let mut iter = write.iter();
|
||||
|
||||
let mut first = true;
|
||||
let mut current = iter.next();
|
||||
while let Some(c) = current {
|
||||
let next = iter.next();
|
||||
let is_last = next.is_none();
|
||||
|
||||
self.write_dma_internal(address, c, first, is_last, no_timeout_fn())
|
||||
.await?;
|
||||
first = false;
|
||||
current = next;
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
/// Read.
|
||||
pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
|
||||
where
|
||||
RXDMA: crate::i2c::RxDma<T>,
|
||||
{
|
||||
let timeout = self.timeout();
|
||||
|
||||
if buffer.is_empty() {
|
||||
self.read_internal(address, buffer, false, timeout_fn(self.timeout))
|
||||
self.read_internal(address, buffer, false, timeout)
|
||||
} else {
|
||||
embassy_time::with_timeout(
|
||||
self.timeout,
|
||||
self.read_dma_internal(address, buffer, false, timeout_fn(self.timeout)),
|
||||
)
|
||||
.await
|
||||
.unwrap_or(Err(Error::Timeout))
|
||||
let fut = self.read_dma_internal(address, buffer, false, timeout);
|
||||
timeout.with(fut).await
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
|
||||
where
|
||||
RXDMA: crate::i2c::RxDma<T>,
|
||||
{
|
||||
if buffer.is_empty() {
|
||||
self.read_internal(address, buffer, false, no_timeout_fn())
|
||||
} else {
|
||||
self.read_dma_internal(address, buffer, false, no_timeout_fn()).await
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
/// Write, restart, read.
|
||||
pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error>
|
||||
where
|
||||
TXDMA: super::TxDma<T>,
|
||||
RXDMA: super::RxDma<T>,
|
||||
{
|
||||
let start_instant = Instant::now();
|
||||
let check_timeout = timeout_fn(self.timeout);
|
||||
let timeout = self.timeout();
|
||||
|
||||
if write.is_empty() {
|
||||
self.write_internal(address, write, false, &check_timeout)?;
|
||||
self.write_internal(address, write, false, timeout)?;
|
||||
} else {
|
||||
embassy_time::with_timeout(
|
||||
self.timeout,
|
||||
self.write_dma_internal(address, write, true, true, &check_timeout),
|
||||
)
|
||||
.await
|
||||
.unwrap_or(Err(Error::Timeout))?;
|
||||
}
|
||||
|
||||
let time_left_until_timeout = self.timeout - Instant::now().duration_since(start_instant);
|
||||
|
||||
if read.is_empty() {
|
||||
self.read_internal(address, read, true, &check_timeout)?;
|
||||
} else {
|
||||
embassy_time::with_timeout(
|
||||
time_left_until_timeout,
|
||||
self.read_dma_internal(address, read, true, &check_timeout),
|
||||
)
|
||||
.await
|
||||
.unwrap_or(Err(Error::Timeout))?;
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error>
|
||||
where
|
||||
TXDMA: super::TxDma<T>,
|
||||
RXDMA: super::RxDma<T>,
|
||||
{
|
||||
let no_timeout = no_timeout_fn();
|
||||
if write.is_empty() {
|
||||
self.write_internal(address, write, false, &no_timeout)?;
|
||||
} else {
|
||||
self.write_dma_internal(address, write, true, true, &no_timeout).await?;
|
||||
let fut = self.write_dma_internal(address, write, true, true, timeout);
|
||||
timeout.with(fut).await?;
|
||||
}
|
||||
|
||||
if read.is_empty() {
|
||||
self.read_internal(address, read, true, &no_timeout)?;
|
||||
self.read_internal(address, read, true, timeout)?;
|
||||
} else {
|
||||
self.read_dma_internal(address, read, true, &no_timeout).await?;
|
||||
let fut = self.read_dma_internal(address, read, true, timeout);
|
||||
timeout.with(fut).await?;
|
||||
}
|
||||
|
||||
Ok(())
|
||||
@ -763,105 +560,35 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
// =========================
|
||||
// Blocking public API
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
pub fn blocking_read_timeout(&mut self, address: u8, read: &mut [u8], timeout: Duration) -> Result<(), Error> {
|
||||
self.read_internal(address, read, false, timeout_fn(timeout))
|
||||
// Automatic Stop
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn blocking_read_timeout(
|
||||
&mut self,
|
||||
address: u8,
|
||||
read: &mut [u8],
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
self.read_internal(address, read, false, check_timeout)
|
||||
// Automatic Stop
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
/// Blocking read.
|
||||
pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
|
||||
self.blocking_read_timeout(address, read, self.timeout)
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
|
||||
self.blocking_read_timeout(address, read, || Ok(()))
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
pub fn blocking_write_timeout(&mut self, address: u8, write: &[u8], timeout: Duration) -> Result<(), Error> {
|
||||
self.write_internal(address, write, true, timeout_fn(timeout))
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn blocking_write_timeout(
|
||||
&mut self,
|
||||
address: u8,
|
||||
write: &[u8],
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
self.write_internal(address, write, true, check_timeout)
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
|
||||
self.blocking_write_timeout(address, write, self.timeout)
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
|
||||
self.blocking_write_timeout(address, write, || Ok(()))
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
pub fn blocking_write_read_timeout(
|
||||
&mut self,
|
||||
address: u8,
|
||||
write: &[u8],
|
||||
read: &mut [u8],
|
||||
timeout: Duration,
|
||||
) -> Result<(), Error> {
|
||||
let check_timeout = timeout_fn(timeout);
|
||||
self.write_internal(address, write, false, &check_timeout)?;
|
||||
self.read_internal(address, read, true, &check_timeout)
|
||||
self.read_internal(address, read, false, self.timeout())
|
||||
// Automatic Stop
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn blocking_write_read_timeout(
|
||||
&mut self,
|
||||
address: u8,
|
||||
write: &[u8],
|
||||
read: &mut [u8],
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
self.write_internal(address, write, false, &check_timeout)?;
|
||||
self.read_internal(address, read, true, &check_timeout)
|
||||
/// Blocking write.
|
||||
pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
|
||||
self.write_internal(address, write, true, self.timeout())
|
||||
}
|
||||
|
||||
/// Blocking write, restart, read.
|
||||
pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
|
||||
let timeout = self.timeout();
|
||||
self.write_internal(address, write, false, timeout)?;
|
||||
self.read_internal(address, read, true, timeout)
|
||||
// Automatic Stop
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
|
||||
self.blocking_write_read_timeout(address, write, read, self.timeout)
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
|
||||
self.blocking_write_read_timeout(address, write, read, || Ok(()))
|
||||
}
|
||||
|
||||
fn blocking_write_vectored_with_timeout(
|
||||
&mut self,
|
||||
address: u8,
|
||||
write: &[&[u8]],
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
/// Blocking write multiple buffers.
|
||||
///
|
||||
/// The buffers are concatenated in a single write transaction.
|
||||
pub fn blocking_write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> {
|
||||
if write.is_empty() {
|
||||
return Err(Error::ZeroLengthTransfer);
|
||||
}
|
||||
|
||||
let timeout = self.timeout();
|
||||
|
||||
let first_length = write[0].len();
|
||||
let last_slice_index = write.len() - 1;
|
||||
|
||||
@ -870,7 +597,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
first_length.min(255),
|
||||
Stop::Software,
|
||||
(first_length > 255) || (last_slice_index != 0),
|
||||
&check_timeout,
|
||||
timeout,
|
||||
) {
|
||||
self.master_stop();
|
||||
return Err(err);
|
||||
@ -890,7 +617,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
if let Err(err) = Self::master_continue(
|
||||
slice_len.min(255),
|
||||
(idx != last_slice_index) || (slice_len > 255),
|
||||
&check_timeout,
|
||||
timeout,
|
||||
) {
|
||||
self.master_stop();
|
||||
return Err(err);
|
||||
@ -902,7 +629,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
if let Err(err) = Self::master_continue(
|
||||
chunk.len(),
|
||||
(number != last_chunk_idx) || (idx != last_slice_index),
|
||||
&check_timeout,
|
||||
timeout,
|
||||
) {
|
||||
self.master_stop();
|
||||
return Err(err);
|
||||
@ -913,7 +640,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
// Wait until we are allowed to send data
|
||||
// (START has been ACKed or last byte when
|
||||
// through)
|
||||
if let Err(err) = self.wait_txe(&check_timeout) {
|
||||
if let Err(err) = self.wait_txe(timeout) {
|
||||
self.master_stop();
|
||||
return Err(err);
|
||||
}
|
||||
@ -925,41 +652,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
}
|
||||
}
|
||||
// Wait until the write finishes
|
||||
let result = self.wait_tc(&check_timeout);
|
||||
let result = self.wait_tc(timeout);
|
||||
self.master_stop();
|
||||
result
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
pub fn blocking_write_vectored_timeout(
|
||||
&mut self,
|
||||
address: u8,
|
||||
write: &[&[u8]],
|
||||
timeout: Duration,
|
||||
) -> Result<(), Error> {
|
||||
let check_timeout = timeout_fn(timeout);
|
||||
self.blocking_write_vectored_with_timeout(address, write, check_timeout)
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn blocking_write_vectored_timeout(
|
||||
&mut self,
|
||||
address: u8,
|
||||
write: &[&[u8]],
|
||||
check_timeout: impl Fn() -> Result<(), Error>,
|
||||
) -> Result<(), Error> {
|
||||
self.blocking_write_vectored_with_timeout(address, write, check_timeout)
|
||||
}
|
||||
|
||||
#[cfg(feature = "time")]
|
||||
pub fn blocking_write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> {
|
||||
self.blocking_write_vectored_timeout(address, write, self.timeout)
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "time"))]
|
||||
pub fn blocking_write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> {
|
||||
self.blocking_write_vectored_timeout(address, write, || Ok(()))
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user