From 9223b67306fcdf41b03d2a9e5d833e5b71b44954 Mon Sep 17 00:00:00 2001 From: Mathias Date: Tue, 11 Oct 2022 10:28:28 +0200 Subject: [PATCH] Fix RTC for v2l0 & v2l1 --- embassy-stm32/src/rtc/v2/v2l0.rs | 46 +++++++++++--------------------- embassy-stm32/src/rtc/v2/v2l1.rs | 44 ++++++++++-------------------- embassy-stm32/src/rtc/v3.rs | 3 ++- 3 files changed, 32 insertions(+), 61 deletions(-) diff --git a/embassy-stm32/src/rtc/v2/v2l0.rs b/embassy-stm32/src/rtc/v2/v2l0.rs index 8d800588..dbd3b088 100644 --- a/embassy-stm32/src/rtc/v2/v2l0.rs +++ b/embassy-stm32/src/rtc/v2/v2l0.rs @@ -1,40 +1,26 @@ pub const BACKUP_REGISTER_COUNT: usize = 20; /// Unlock the backup domain -pub(super) unsafe fn unlock_backup_domain(_clock_config: u8) { - // FIXME: - // crate::pac::PWR.cr1().modify(|w| w.set_dbp(true)); - // while !crate::pac::PWR.cr1().read().dbp() {} +pub(super) unsafe fn unlock_backup_domain(clock_config: u8) { + // TODO: Missing from PAC? + // crate::pac::PWR.cr().modify(|w| w.set_dbp(true)); + // while !crate::pac::PWR.cr().read().dbp() {} - // let reg = crate::pac::RCC.bdcr().read(); - // assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet."); + let reg = crate::pac::RCC.csr().read(); - // if !reg.rtcen() || reg.rtcsel().0 != clock_config { - // crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); + if !reg.rtcen() || reg.rtcsel().0 != clock_config { + crate::pac::RCC.csr().modify(|w| { + // Select RTC source + w.set_rtcsel(crate::pac::rcc::vals::Rtcsel(clock_config)); + w.set_rtcen(true); - // crate::pac::RCC.bdcr().modify(|w| { - // // Reset - // w.set_bdrst(false); - - // // Select RTC source - // w.set_rtcsel(Rtcsel(clock_config)); - // w.set_rtcen(true); - - // // Restore bcdr - // w.set_lscosel(reg.lscosel()); - // w.set_lscoen(reg.lscoen()); - - // w.set_lseon(reg.lseon()); - // w.set_lsedrv(reg.lsedrv()); - // w.set_lsebyp(reg.lsebyp()); - // }); - // } + w.set_lseon(reg.lseon()); + w.set_lsedrv(reg.lsedrv()); + w.set_lsebyp(reg.lsebyp()); + }); + } } pub(crate) unsafe fn enable_peripheral_clk() { - // // enable peripheral clock for communication - // crate::pac::rcc.apb1enr1().modify(|w| w.set_rtcapben(true)); - - // // read to allow the pwr clock to enable - // crate::pac::PWR.cr1().read(); + // Nothing to do } diff --git a/embassy-stm32/src/rtc/v2/v2l1.rs b/embassy-stm32/src/rtc/v2/v2l1.rs index 8d800588..1ac78b31 100644 --- a/embassy-stm32/src/rtc/v2/v2l1.rs +++ b/embassy-stm32/src/rtc/v2/v2l1.rs @@ -1,40 +1,24 @@ pub const BACKUP_REGISTER_COUNT: usize = 20; /// Unlock the backup domain -pub(super) unsafe fn unlock_backup_domain(_clock_config: u8) { - // FIXME: - // crate::pac::PWR.cr1().modify(|w| w.set_dbp(true)); - // while !crate::pac::PWR.cr1().read().dbp() {} +pub(super) unsafe fn unlock_backup_domain(clock_config: u8) { + crate::pac::PWR.cr().modify(|w| w.set_dbp(true)); + while !crate::pac::PWR.cr().read().dbp() {} - // let reg = crate::pac::RCC.bdcr().read(); - // assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet."); + let reg = crate::pac::RCC.csr().read(); - // if !reg.rtcen() || reg.rtcsel().0 != clock_config { - // crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); + if !reg.rtcen() || reg.rtcsel().0 != clock_config { + crate::pac::RCC.csr().modify(|w| { + // Select RTC source + w.set_rtcsel(crate::pac::rcc::vals::Rtcsel(clock_config)); + w.set_rtcen(true); - // crate::pac::RCC.bdcr().modify(|w| { - // // Reset - // w.set_bdrst(false); - - // // Select RTC source - // w.set_rtcsel(Rtcsel(clock_config)); - // w.set_rtcen(true); - - // // Restore bcdr - // w.set_lscosel(reg.lscosel()); - // w.set_lscoen(reg.lscoen()); - - // w.set_lseon(reg.lseon()); - // w.set_lsedrv(reg.lsedrv()); - // w.set_lsebyp(reg.lsebyp()); - // }); - // } + w.set_lseon(reg.lseon()); + w.set_lsebyp(reg.lsebyp()); + }); + } } pub(crate) unsafe fn enable_peripheral_clk() { - // // enable peripheral clock for communication - // crate::pac::rcc.apb1enr1().modify(|w| w.set_rtcapben(true)); - - // // read to allow the pwr clock to enable - // crate::pac::PWR.cr1().read(); + // Nothing to do } diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs index dfe27ed6..c9a794c3 100644 --- a/embassy-stm32/src/rtc/v3.rs +++ b/embassy-stm32/src/rtc/v3.rs @@ -32,7 +32,8 @@ impl<'d, T: Instance> super::Rtc<'d, T> { feature = "stm32wl54jc-cm0p", feature = "stm32wle5ub", feature = "stm32g0c1ve", - feature = "stm32wl55jc-cm4" + feature = "stm32wl55jc-cm4", + feature = "stm32wl55uc-cm4" )))] let config_rtcsel = stm32_metapac::rtc::vals::Rtcsel(config_rtcsel); #[cfg(feature = "stm32g0c1ve")]