Add minimal RCC impls for L4 and F4

embassy-stm32/src/rcc/l0/mod.rs

@@ -1,6 +1,7 @@
+pub use super::common::*;
 use crate::pac;
 use crate::peripherals::{self, CRS, RCC, SYSCFG};
-use crate::rcc::{get_freqs, set_freqs};
+use crate::rcc::{get_freqs, set_freqs, Clocks};
 use crate::time::Hertz;
 use crate::time::U32Ext;
 use core::marker::PhantomData;
@@ -12,13 +13,8 @@ use pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
 /// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
 /// and with the addition of the init function to configure a system clock.
 
-#[derive(Clone, Copy)]
-pub struct Clocks {
-    pub sys: Hertz,
-    pub ahb: Hertz,
-    pub apb1: Hertz,
-    pub apb2: Hertz,
-}
+/// HSI speed
+pub const HSI_FREQ: u32 = 16_000_000;
 
 /// System clock mux source
 #[derive(Clone, Copy)]
@@ -29,90 +25,6 @@ pub enum ClockSrc {
     HSI16,
 }
 
-/// MSI Clock Range
-///
-/// These ranges control the frequency of the MSI. Internally, these ranges map
-/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
-#[derive(Clone, Copy)]
-pub enum MSIRange {
-    /// Around 65.536 kHz
-    Range0,
-    /// Around 131.072 kHz
-    Range1,
-    /// Around 262.144 kHz
-    Range2,
-    /// Around 524.288 kHz
-    Range3,
-    /// Around 1.048 MHz
-    Range4,
-    /// Around 2.097 MHz (reset value)
-    Range5,
-    /// Around 4.194 MHz
-    Range6,
-}
-
-impl Default for MSIRange {
-    fn default() -> MSIRange {
-        MSIRange::Range5
-    }
-}
-
-/// PLL divider
-#[derive(Clone, Copy)]
-pub enum PLLDiv {
-    Div2,
-    Div3,
-    Div4,
-}
-
-/// PLL multiplier
-#[derive(Clone, Copy)]
-pub enum PLLMul {
-    Mul3,
-    Mul4,
-    Mul6,
-    Mul8,
-    Mul12,
-    Mul16,
-    Mul24,
-    Mul32,
-    Mul48,
-}
-
-/// AHB prescaler
-#[derive(Clone, Copy)]
-pub enum AHBPrescaler {
-    NotDivided,
-    Div2,
-    Div4,
-    Div8,
-    Div16,
-    Div64,
-    Div128,
-    Div256,
-    Div512,
-}
-
-/// APB prescaler
-#[derive(Clone, Copy)]
-pub enum APBPrescaler {
-    NotDivided,
-    Div2,
-    Div4,
-    Div8,
-    Div16,
-}
-
-/// PLL clock input source
-#[derive(Clone, Copy)]
-pub enum PLLSource {
-    HSI16,
-    HSE(Hertz),
-}
-
-/// HSI speed
-pub const HSI_FREQ: u32 = 16_000_000;
-
 impl Into<Pllmul> for PLLMul {
     fn into(self) -> Pllmul {
         match self {