diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index 3e793f39..c9c9cb25 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -274,9 +274,9 @@ impl<'d, T: Instance> Spim<'d, T> {
             Ok(_) => Ok(()),
             Err(Error::DMABufferNotInDataMemory) => {
                 trace!("Copying SPIM tx buffer into RAM for DMA");
-                let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE];
-                tx_buf[..tx.len()].copy_from_slice(tx);
-                self.blocking_inner_from_ram(rx, &tx_buf[..tx.len()])
+                let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
+                tx_ram_buf.copy_from_slice(tx);
+                self.blocking_inner_from_ram(rx, tx_ram_buf)
             }
             Err(error) => Err(error),
         }
@@ -306,9 +306,9 @@ impl<'d, T: Instance> Spim<'d, T> {
             Ok(_) => Ok(()),
             Err(Error::DMABufferNotInDataMemory) => {
                 trace!("Copying SPIM tx buffer into RAM for DMA");
-                let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE];
-                tx_buf[..tx.len()].copy_from_slice(tx);
-                self.async_inner_from_ram(rx, &tx_buf[..tx.len()]).await
+                let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
+                tx_ram_buf.copy_from_slice(tx);
+                self.async_inner_from_ram(rx, tx_ram_buf).await
             }
             Err(error) => Err(error),
         }
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index 675029a8..c8ad2a0e 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -398,14 +398,9 @@ impl<'d, T: Instance> Twim<'d, T> {
             Ok(_) => Ok(()),
             Err(Error::DMABufferNotInDataMemory) => {
                 trace!("Copying TWIM tx buffer into RAM for DMA");
-                let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE];
-                tx_buf[..wr_buffer.len()].copy_from_slice(wr_buffer);
-                self.setup_write_read_from_ram(
-                    address,
-                    &tx_buf[..wr_buffer.len()],
-                    rd_buffer,
-                    inten,
-                )
+                let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
+                tx_ram_buf.copy_from_slice(wr_buffer);
+                self.setup_write_read_from_ram(address, &tx_ram_buf, rd_buffer, inten)
             }
             Err(error) => Err(error),
         }
@@ -416,9 +411,9 @@ impl<'d, T: Instance> Twim<'d, T> {
             Ok(_) => Ok(()),
             Err(Error::DMABufferNotInDataMemory) => {
                 trace!("Copying TWIM tx buffer into RAM for DMA");
-                let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE];
-                tx_buf[..wr_buffer.len()].copy_from_slice(wr_buffer);
-                self.setup_write_from_ram(address, &tx_buf[..wr_buffer.len()], inten)
+                let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
+                tx_ram_buf.copy_from_slice(wr_buffer);
+                self.setup_write_from_ram(address, &tx_ram_buf, inten)
             }
             Err(error) => Err(error),
         }
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 4aa1f02d..7d7b904b 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -247,9 +247,9 @@ impl<'d, T: Instance> UarteTx<'d, T> {
             Ok(_) => Ok(()),
             Err(Error::DMABufferNotInDataMemory) => {
                 trace!("Copying UARTE tx buffer into RAM for DMA");
-                let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE];
-                tx_buf[..buffer.len()].copy_from_slice(buffer);
-                self.write_from_ram(&tx_buf[..buffer.len()]).await
+                let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
+                ram_buf.copy_from_slice(buffer);
+                self.write_from_ram(&ram_buf).await
             }
             Err(error) => Err(error),
         }
@@ -314,9 +314,9 @@ impl<'d, T: Instance> UarteTx<'d, T> {
             Ok(_) => Ok(()),
             Err(Error::DMABufferNotInDataMemory) => {
                 trace!("Copying UARTE tx buffer into RAM for DMA");
-                let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE];
-                tx_buf[..buffer.len()].copy_from_slice(buffer);
-                self.blocking_write_from_ram(&tx_buf[..buffer.len()])
+                let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
+                ram_buf.copy_from_slice(buffer);
+                self.blocking_write_from_ram(&ram_buf)
             }
             Err(error) => Err(error),
         }