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Make RCC lookup optional

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This commit is contained in:
Ulf Lilleengen 2021-06-09 18:48:32 +02:00
parent f3d1ac6623
commit 9a2adec584
1 changed files with 37 additions and 28 deletions
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65
stm32-metapac/build.rs
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@ -156,12 +156,19 @@ fn main() {
}; };
// Load RCC register for chip // Load RCC register for chip
let chip_family = chip.family.to_ascii_lowercase(); let rcc = chip.peripherals.iter().find_map(|(name, p)| {
let rcc_family = chip_family.strip_prefix("stm32").unwrap(); if name == "RCC" {
let rcc_reg_path = Path::new(&dir) p.block.as_ref().map(|block| {
.join("registers") let bi = BlockInfo::parse(block);
.join(&format!("rcc_{}.yaml", &rcc_family[0..2])); let rcc_reg_path = Path::new(&dir)
let rcc: ir::IR = serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap(); .join("registers")
.join(&format!("{}_{}.yaml", bi.module, bi.version));
serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap()
})
} else {
None
}
});
let mut peripheral_versions: HashMap<String, String> = HashMap::new(); let mut peripheral_versions: HashMap<String, String> = HashMap::new();
let mut pin_table: Vec<Vec<String>> = Vec::new(); let mut pin_table: Vec<Vec<String>> = Vec::new();
@ -254,29 +261,31 @@ fn main() {
} }
if let Some(clock) = &p.clock { if let Some(clock) = &p.clock {
// Workaround for clock registers being split on some chip families. Assume fields are if let Some(rcc) = &rcc {
// named after peripheral and look for first field matching and use that register. // Workaround for clock registers being split on some chip families. Assume fields are
let en = find_reg_for_field(&rcc, clock, &format!("{}EN", name)); // named after peripheral and look for first field matching and use that register.
let rst = find_reg_for_field(&rcc, clock, &format!("{}RST", name)); let en = find_reg_for_field(&rcc, clock, &format!("{}EN", name));
let rst = find_reg_for_field(&rcc, clock, &format!("{}RST", name));
match (en, rst) { match (en, rst) {
(Some((enable_reg, enable_field)), Some((reset_reg, reset_field))) => { (Some((enable_reg, enable_field)), Some((reset_reg, reset_field))) => {
peripheral_rcc_table.push(vec![ peripheral_rcc_table.push(vec![
name.clone(), name.clone(),
enable_reg.to_ascii_lowercase(), enable_reg.to_ascii_lowercase(),
reset_reg.to_ascii_lowercase(), reset_reg.to_ascii_lowercase(),
format!("set_{}", enable_field.to_ascii_lowercase()), format!("set_{}", enable_field.to_ascii_lowercase()),
format!("set_{}", reset_field.to_ascii_lowercase()), format!("set_{}", reset_field.to_ascii_lowercase()),
]); ]);
} }
(None, Some(_)) => { (None, Some(_)) => {
println!("Unable to find enable register for {}", name) println!("Unable to find enable register for {}", name)
} }
(Some(_), None) => { (Some(_), None) => {
println!("Unable to find reset register for {}", name) println!("Unable to find reset register for {}", name)
} }
(None, None) => { (None, None) => {
println!("Unable to find enable and reset register for {}", name) println!("Unable to find enable and reset register for {}", name)
}
} }
} }
} }