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Dario Nieuwenhuis
2020-09-22 18:03:43 +02:00
commit 9a57deef9b
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131
embassy-nrf/src/interrupt.rs Normal file
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//! Interrupt management
//!
//! This module implements an API for managing interrupts compatible with
//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time.
use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
use crate::pac::{NVIC, NVIC_PRIO_BITS};
// Re-exports
pub use crate::pac::Interrupt;
pub use crate::pac::Interrupt::*; // needed for cortex-m-rt #[interrupt]
pub use bare_metal::{CriticalSection, Mutex};
#[derive(defmt::Format, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
#[repr(u8)]
pub enum Priority {
Level0 = 0,
Level1 = 1,
Level2 = 2,
Level3 = 3,
Level4 = 4,
Level5 = 5,
Level6 = 6,
Level7 = 7,
}
impl Priority {
#[inline]
fn to_nvic(self) -> u8 {
(self as u8) << (8 - NVIC_PRIO_BITS)
}
#[inline]
fn from_nvic(priority: u8) -> Self {
match priority >> (8 - NVIC_PRIO_BITS) {
0 => Self::Level0,
1 => Self::Level1,
2 => Self::Level2,
3 => Self::Level3,
4 => Self::Level4,
5 => Self::Level5,
6 => Self::Level6,
7 => Self::Level7,
_ => unreachable!(),
}
}
}
static CS_FLAG: AtomicBool = AtomicBool::new(false);
static mut CS_MASK: [u32; 2] = [0; 2];
#[inline]
pub fn free<F, R>(f: F) -> R
where
F: FnOnce(&CriticalSection) -> R,
{
unsafe {
// TODO: assert that we're in privileged level
// Needed because disabling irqs in non-privileged level is a noop, which would break safety.
let primask: u32;
asm!("mrs {}, PRIMASK", out(reg) primask);
asm!("cpsid i");
// Prevent compiler from reordering operations inside/outside the critical section.
compiler_fence(Ordering::SeqCst);
let r = f(&CriticalSection::new());
compiler_fence(Ordering::SeqCst);
if primask & 1 == 0 {
asm!("cpsie i");
}
r
}
}
#[inline]
pub fn enable(irq: Interrupt) {
unsafe {
NVIC::unmask(irq);
}
}
#[inline]
pub fn disable(irq: Interrupt) {
NVIC::mask(irq);
}
#[inline]
pub fn is_active(irq: Interrupt) -> bool {
NVIC::is_active(irq)
}
#[inline]
pub fn is_enabled(irq: Interrupt) -> bool {
NVIC::is_enabled(irq)
}
#[inline]
pub fn is_pending(irq: Interrupt) -> bool {
NVIC::is_pending(irq)
}
#[inline]
pub fn pend(irq: Interrupt) {
NVIC::pend(irq)
}
#[inline]
pub fn unpend(irq: Interrupt) {
NVIC::unpend(irq)
}
#[inline]
pub fn get_priority(irq: Interrupt) -> Priority {
Priority::from_nvic(NVIC::get_priority(irq))
}
#[inline]
pub fn set_priority(irq: Interrupt, prio: Priority) {
unsafe {
cortex_m::peripheral::Peripherals::steal()
.NVIC
.set_priority(irq, prio.to_nvic())
}
}

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embassy-nrf/src/lib.rs Normal file
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#![no_std]
#![feature(generic_associated_types)]
#![feature(asm)]
#![feature(type_alias_impl_trait)]
#[cfg(not(any(
feature = "nrf52810",
feature = "nrf52811",
feature = "nrf52832",
feature = "nrf52833",
feature = "nrf52840",
)))]
compile_error!("No chip feature activated. You must activate exactly one of the following features: nrf52810, nrf52811, nrf52832, nrf52833, nrf52840");
#[cfg(any(
all(feature = "nrf52810", feature = "nrf52811"),
all(feature = "nrf52810", feature = "nrf52832"),
all(feature = "nrf52810", feature = "nrf52833"),
all(feature = "nrf52810", feature = "nrf52840"),
all(feature = "nrf52811", feature = "nrf52832"),
all(feature = "nrf52811", feature = "nrf52833"),
all(feature = "nrf52811", feature = "nrf52840"),
all(feature = "nrf52832", feature = "nrf52833"),
all(feature = "nrf52832", feature = "nrf52840"),
all(feature = "nrf52833", feature = "nrf52840"),
))]
compile_error!("Multile chip features activated. You must activate exactly one of the following features: nrf52810, nrf52811, nrf52832, nrf52833, nrf52840");
#[cfg(feature = "nrf52810")]
pub use nrf52810_pac as pac;
#[cfg(feature = "nrf52811")]
pub use nrf52811_pac as pac;
#[cfg(feature = "nrf52832")]
pub use nrf52832_pac as pac;
#[cfg(feature = "nrf52833")]
pub use nrf52833_pac as pac;
#[cfg(feature = "nrf52840")]
pub use nrf52840_pac as pac;
pub mod interrupt;
pub mod qspi;
pub mod uarte;
pub use cortex_m_rt::interrupt;

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embassy-nrf/src/qspi.rs Normal file
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use crate::pac::{Interrupt, QSPI};
use core::future::Future;
use nrf52840_hal::gpio::{Output, Pin as GpioPin, Port as GpioPort, PushPull};
pub use crate::pac::qspi::ifconfig0::ADDRMODE_A as AddressMode;
pub use crate::pac::qspi::ifconfig0::PPSIZE_A as WritePageSize;
pub use crate::pac::qspi::ifconfig0::READOC_A as ReadOpcode;
pub use crate::pac::qspi::ifconfig0::WRITEOC_A as WriteOpcode;
// TODO
// - config:
// - 32bit address mode
// - SPI freq
// - SPI sck delay
// - Deep power down mode (DPM)
// - SPI mode 3
// - activate/deactivate
// - set gpio in high drive
use embassy::flash::{Error, Flash};
use embassy::util::{DropBomb, Signal};
use crate::interrupt;
pub struct Pins {
pub sck: GpioPin<Output<PushPull>>,
pub csn: GpioPin<Output<PushPull>>,
pub io0: GpioPin<Output<PushPull>>,
pub io1: GpioPin<Output<PushPull>>,
pub io2: Option<GpioPin<Output<PushPull>>>,
pub io3: Option<GpioPin<Output<PushPull>>>,
}
pub struct Config {
pub pins: Pins,
pub xip_offset: u32,
pub read_opcode: ReadOpcode,
pub write_opcode: WriteOpcode,
pub write_page_size: WritePageSize,
}
pub struct Qspi {
inner: QSPI,
}
fn port_bit(port: GpioPort) -> bool {
match port {
GpioPort::Port0 => false,
GpioPort::Port1 => true,
}
}
impl Qspi {
pub fn new(qspi: QSPI, config: Config) -> Self {
qspi.psel.sck.write(|w| {
let pin = &config.pins.sck;
let w = unsafe { w.pin().bits(pin.pin()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
});
qspi.psel.csn.write(|w| {
let pin = &config.pins.csn;
let w = unsafe { w.pin().bits(pin.pin()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
});
qspi.psel.io0.write(|w| {
let pin = &config.pins.io0;
let w = unsafe { w.pin().bits(pin.pin()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
});
qspi.psel.io1.write(|w| {
let pin = &config.pins.io1;
let w = unsafe { w.pin().bits(pin.pin()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
});
qspi.psel.io2.write(|w| {
if let Some(ref pin) = config.pins.io2 {
let w = unsafe { w.pin().bits(pin.pin()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
} else {
w.connect().disconnected()
}
});
qspi.psel.io3.write(|w| {
if let Some(ref pin) = config.pins.io3 {
let w = unsafe { w.pin().bits(pin.pin()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
} else {
w.connect().disconnected()
}
});
qspi.ifconfig0.write(|w| {
let w = w.addrmode().variant(AddressMode::_24BIT);
let w = w.dpmenable().disable();
let w = w.ppsize().variant(config.write_page_size);
let w = w.readoc().variant(config.read_opcode);
let w = w.writeoc().variant(config.write_opcode);
w
});
qspi.ifconfig1.write(|w| {
let w = unsafe { w.sckdelay().bits(80) };
let w = w.dpmen().exit();
let w = w.spimode().mode0();
let w = unsafe { w.sckfreq().bits(3) };
w
});
qspi.xipoffset
.write(|w| unsafe { w.xipoffset().bits(config.xip_offset) });
// Enable it
qspi.enable.write(|w| w.enable().enabled());
qspi.events_ready.reset();
qspi.tasks_activate.write(|w| w.tasks_activate().bit(true));
while qspi.events_ready.read().bits() == 0 {}
qspi.events_ready.reset();
// Enable READY interrupt
qspi.intenset.write(|w| w.ready().set());
interrupt::set_priority(Interrupt::QSPI, interrupt::Priority::Level7);
interrupt::enable(Interrupt::QSPI);
Self { inner: qspi }
}
pub fn custom_instruction<'a>(
&'a mut self,
opcode: u8,
req: &'a [u8],
resp: &'a mut [u8],
) -> impl Future<Output = Result<(), Error>> + 'a {
async move {
let bomb = DropBomb::new();
assert!(req.len() <= 8);
assert!(resp.len() <= 8);
let mut dat0: u32 = 0;
let mut dat1: u32 = 0;
for i in 0..4 {
if i < req.len() {
dat0 |= (req[i] as u32) << (i * 8);
}
}
for i in 0..4 {
if i + 4 < req.len() {
dat1 |= (req[i + 4] as u32) << (i * 8);
}
}
let len = core::cmp::max(req.len(), resp.len()) as u8;
self.inner.cinstrdat0.write(|w| unsafe { w.bits(dat0) });
self.inner.cinstrdat1.write(|w| unsafe { w.bits(dat1) });
self.inner.events_ready.reset();
self.inner.cinstrconf.write(|w| {
let w = unsafe { w.opcode().bits(opcode) };
let w = unsafe { w.length().bits(len + 1) };
let w = w.lio2().bit(true);
let w = w.lio3().bit(true);
let w = w.wipwait().bit(true);
let w = w.wren().bit(true);
let w = w.lfen().bit(false);
let w = w.lfstop().bit(false);
w
});
SIGNAL.wait().await;
let dat0 = self.inner.cinstrdat0.read().bits();
let dat1 = self.inner.cinstrdat1.read().bits();
for i in 0..4 {
if i < resp.len() {
resp[i] = (dat0 >> (i * 8)) as u8;
}
}
for i in 0..4 {
if i + 4 < resp.len() {
resp[i] = (dat1 >> (i * 8)) as u8;
}
}
bomb.defuse();
Ok(())
}
}
}
impl Flash for Qspi {
type ReadFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
type WriteFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
type ErasePageFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
fn read<'a>(&'a mut self, address: usize, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
async move {
let bomb = DropBomb::new();
assert_eq!(data.as_ptr() as u32 % 4, 0);
assert_eq!(data.len() as u32 % 4, 0);
assert_eq!(address as u32 % 4, 0);
self.inner
.read
.src
.write(|w| unsafe { w.src().bits(address as u32) });
self.inner
.read
.dst
.write(|w| unsafe { w.dst().bits(data.as_ptr() as u32) });
self.inner
.read
.cnt
.write(|w| unsafe { w.cnt().bits(data.len() as u32) });
self.inner.events_ready.reset();
self.inner
.tasks_readstart
.write(|w| w.tasks_readstart().bit(true));
SIGNAL.wait().await;
bomb.defuse();
Ok(())
}
}
fn write<'a>(&'a mut self, address: usize, data: &'a [u8]) -> Self::WriteFuture<'a> {
async move {
let bomb = DropBomb::new();
assert_eq!(data.as_ptr() as u32 % 4, 0);
assert_eq!(data.len() as u32 % 4, 0);
assert_eq!(address as u32 % 4, 0);
self.inner
.write
.src
.write(|w| unsafe { w.src().bits(data.as_ptr() as u32) });
self.inner
.write
.dst
.write(|w| unsafe { w.dst().bits(address as u32) });
self.inner
.write
.cnt
.write(|w| unsafe { w.cnt().bits(data.len() as u32) });
self.inner.events_ready.reset();
self.inner
.tasks_writestart
.write(|w| w.tasks_writestart().bit(true));
SIGNAL.wait().await;
bomb.defuse();
Ok(())
}
}
fn erase<'a>(&'a mut self, address: usize) -> Self::ErasePageFuture<'a> {
async move {
let bomb = DropBomb::new();
assert_eq!(address as u32 % 4096, 0);
self.inner
.erase
.ptr
.write(|w| unsafe { w.ptr().bits(address as u32) });
self.inner.erase.len.write(|w| w.len()._4kb());
self.inner.events_ready.reset();
self.inner
.tasks_erasestart
.write(|w| w.tasks_erasestart().bit(true));
SIGNAL.wait().await;
bomb.defuse();
Ok(())
}
}
fn size(&self) -> usize {
256 * 4096 // TODO
}
fn read_size(&self) -> usize {
4 // TODO
}
fn write_size(&self) -> usize {
4 // TODO
}
fn erase_size(&self) -> usize {
4096 // TODO
}
}
static SIGNAL: Signal<()> = Signal::new();
#[interrupt]
unsafe fn QSPI() {
let p = unsafe { crate::pac::Peripherals::steal().QSPI };
if p.events_ready.read().events_ready().bit_is_set() {
p.events_ready.reset();
SIGNAL.signal(());
}
}

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embassy-nrf/src/uarte.rs Normal file
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//! HAL interface to the UARTE peripheral
//!
//! See product specification:
//!
//! - nrf52832: Section 35
//! - nrf52840: Section 6.34
use core::cell::UnsafeCell;
use core::cmp::min;
use core::marker::PhantomPinned;
use core::ops::Deref;
use core::pin::Pin;
use core::ptr;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll};
use crate::interrupt;
use crate::interrupt::CriticalSection;
use crate::pac::{uarte0, Interrupt, UARTE0, UARTE1};
use embedded_hal::digital::v2::OutputPin;
use nrf52840_hal::gpio::{Floating, Input, Output, Pin as GpioPin, Port as GpioPort, PushPull};
// Re-export SVD variants to allow user to directly set values
pub use uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
use embassy::io::{AsyncBufRead, AsyncWrite, Result};
use embassy::util::WakerStore;
use defmt::trace;
//use crate::trace;
const RINGBUF_SIZE: usize = 512;
struct RingBuf {
buf: [u8; RINGBUF_SIZE],
start: usize,
end: usize,
empty: bool,
}
impl RingBuf {
fn new() -> Self {
RingBuf {
buf: [0; RINGBUF_SIZE],
start: 0,
end: 0,
empty: true,
}
}
fn push_buf(&mut self) -> &mut [u8] {
if self.start == self.end && !self.empty {
trace!(" ringbuf: push_buf empty");
return &mut self.buf[..0];
}
let n = if self.start <= self.end {
RINGBUF_SIZE - self.end
} else {
self.start - self.end
};
trace!(" ringbuf: push_buf {:?}..{:?}", self.end, self.end + n);
&mut self.buf[self.end..self.end + n]
}
fn push(&mut self, n: usize) {
trace!(" ringbuf: push {:?}", n);
if n == 0 {
return;
}
self.end = Self::wrap(self.end + n);
self.empty = false;
}
fn pop_buf(&mut self) -> &mut [u8] {
if self.empty {
trace!(" ringbuf: pop_buf empty");
return &mut self.buf[..0];
}
let n = if self.end <= self.start {
RINGBUF_SIZE - self.start
} else {
self.end - self.start
};
trace!(" ringbuf: pop_buf {:?}..{:?}", self.start, self.start + n);
&mut self.buf[self.start..self.start + n]
}
fn pop(&mut self, n: usize) {
trace!(" ringbuf: pop {:?}", n);
if n == 0 {
return;
}
self.start = Self::wrap(self.start + n);
self.empty = self.start == self.end;
}
fn wrap(n: usize) -> usize {
assert!(n <= RINGBUF_SIZE);
if n == RINGBUF_SIZE {
0
} else {
n
}
}
}
#[derive(Copy, Clone, Debug, PartialEq)]
enum RxState {
Idle,
Receiving,
ReceivingReady,
Stopping,
}
#[derive(Copy, Clone, Debug, PartialEq)]
enum TxState {
Idle,
Transmitting(usize),
}
/// Interface to a UARTE instance
///
/// This is a very basic interface that comes with the following limitations:
/// - The UARTE instances share the same address space with instances of UART.
/// You need to make sure that conflicting instances
/// are disabled before using `Uarte`. See product specification:
/// - nrf52832: Section 15.2
/// - nrf52840: Section 6.1.2
pub struct Uarte<T: Instance> {
started: bool,
state: UnsafeCell<UarteState<T>>,
}
// public because it needs to be used in Instance::{get_state, set_state}, but
// should not be used outside the module
#[doc(hidden)]
pub struct UarteState<T> {
inner: T,
rx: RingBuf,
rx_state: RxState,
rx_waker: WakerStore,
tx: RingBuf,
tx_state: TxState,
tx_waker: WakerStore,
_pin: PhantomPinned,
}
fn port_bit(port: GpioPort) -> bool {
match port {
GpioPort::Port0 => false,
GpioPort::Port1 => true,
}
}
impl<T: Instance> Uarte<T> {
pub fn new(uarte: T, mut pins: Pins, parity: Parity, baudrate: Baudrate) -> Self {
// Select pins
uarte.psel.rxd.write(|w| {
let w = unsafe { w.pin().bits(pins.rxd.pin()) };
let w = w.port().bit(port_bit(pins.rxd.port()));
w.connect().connected()
});
pins.txd.set_high().unwrap();
uarte.psel.txd.write(|w| {
let w = unsafe { w.pin().bits(pins.txd.pin()) };
let w = w.port().bit(port_bit(pins.txd.port()));
w.connect().connected()
});
// Optional pins
uarte.psel.cts.write(|w| {
if let Some(ref pin) = pins.cts {
let w = unsafe { w.pin().bits(pin.pin()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
} else {
w.connect().disconnected()
}
});
uarte.psel.rts.write(|w| {
if let Some(ref pin) = pins.rts {
let w = unsafe { w.pin().bits(pin.pin()) };
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
} else {
w.connect().disconnected()
}
});
// Enable UARTE instance
uarte.enable.write(|w| w.enable().enabled());
// Enable interrupts
uarte.intenset.write(|w| w.endrx().set().endtx().set());
// Configure
let hardware_flow_control = pins.rts.is_some() && pins.cts.is_some();
uarte
.config
.write(|w| w.hwfc().bit(hardware_flow_control).parity().variant(parity));
// Configure frequency
uarte.baudrate.write(|w| w.baudrate().variant(baudrate));
Uarte {
started: false,
state: UnsafeCell::new(UarteState {
inner: uarte,
rx: RingBuf::new(),
rx_state: RxState::Idle,
rx_waker: WakerStore::new(),
tx: RingBuf::new(),
tx_state: TxState::Idle,
tx_waker: WakerStore::new(),
_pin: PhantomPinned,
}),
}
}
fn with_state<'a, R>(
self: Pin<&'a mut Self>,
f: impl FnOnce(Pin<&'a mut UarteState<T>>) -> R,
) -> R {
let Self { state, started } = unsafe { self.get_unchecked_mut() };
interrupt::free(|cs| {
let ptr = state.get();
if !*started {
T::set_state(cs, ptr);
*started = true;
// safety: safe because critical section ensures only one *mut UartState
// exists at the same time.
unsafe { Pin::new_unchecked(&mut *ptr) }.start();
}
// safety: safe because critical section ensures only one *mut UartState
// exists at the same time.
f(unsafe { Pin::new_unchecked(&mut *ptr) })
})
}
}
impl<T: Instance> Drop for Uarte<T> {
fn drop(&mut self) {
// stop DMA before dropping, because DMA is using the buffer in `self`.
todo!()
}
}
impl<T: Instance> AsyncBufRead for Uarte<T> {
fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Result<&[u8]>> {
self.with_state(|s| s.poll_fill_buf(cx))
}
fn consume(self: Pin<&mut Self>, amt: usize) {
self.with_state(|s| s.consume(amt))
}
}
impl<T: Instance> AsyncWrite for Uarte<T> {
fn poll_write(self: Pin<&mut Self>, cx: &mut Context<'_>, buf: &[u8]) -> Poll<Result<usize>> {
self.with_state(|s| s.poll_write(cx, buf))
}
}
impl<T: Instance> UarteState<T> {
pub fn start(self: Pin<&mut Self>) {
interrupt::set_priority(T::interrupt(), interrupt::Priority::Level7);
interrupt::enable(T::interrupt());
interrupt::pend(T::interrupt());
}
fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Result<&[u8]>> {
let this = unsafe { self.get_unchecked_mut() };
// Conservative compiler fence to prevent optimizations that do not
// take in to account actions by DMA. The fence has been placed here,
// before any DMA action has started
compiler_fence(Ordering::SeqCst);
trace!("poll_read");
// We have data ready in buffer? Return it.
let buf = this.rx.pop_buf();
if buf.len() != 0 {
trace!(" got {:?} {:?}", buf.as_ptr() as u32, buf.len());
return Poll::Ready(Ok(buf));
}
trace!(" empty");
if this.rx_state == RxState::ReceivingReady {
trace!(" stopping");
this.rx_state = RxState::Stopping;
this.inner.tasks_stoprx.write(|w| unsafe { w.bits(1) });
}
this.rx_waker.store(cx.waker());
Poll::Pending
}
fn consume(self: Pin<&mut Self>, amt: usize) {
let this = unsafe { self.get_unchecked_mut() };
trace!("consume {:?}", amt);
this.rx.pop(amt);
interrupt::pend(T::interrupt());
}
fn poll_write(self: Pin<&mut Self>, cx: &mut Context<'_>, buf: &[u8]) -> Poll<Result<usize>> {
let this = unsafe { self.get_unchecked_mut() };
trace!("poll_write: {:?}", buf.len());
let tx_buf = this.tx.push_buf();
if tx_buf.len() == 0 {
trace!("poll_write: pending");
this.tx_waker.store(cx.waker());
return Poll::Pending;
}
let n = min(tx_buf.len(), buf.len());
tx_buf[..n].copy_from_slice(&buf[..n]);
this.tx.push(n);
trace!("poll_write: queued {:?}", n);
// Conservative compiler fence to prevent optimizations that do not
// take in to account actions by DMA. The fence has been placed here,
// before any DMA action has started
compiler_fence(Ordering::SeqCst);
interrupt::pend(T::interrupt());
Poll::Ready(Ok(n))
}
fn on_interrupt(&mut self) {
trace!("irq: start");
let mut more_work = true;
while more_work {
more_work = false;
match self.rx_state {
RxState::Idle => {
trace!(" irq_rx: in state idle");
if self.inner.events_rxdrdy.read().bits() != 0 {
trace!(" irq_rx: rxdrdy?????");
self.inner.events_rxdrdy.reset();
}
if self.inner.events_endrx.read().bits() != 0 {
panic!("unexpected endrx");
}
let buf = self.rx.push_buf();
if buf.len() != 0 {
trace!(" irq_rx: starting {:?}", buf.len());
self.rx_state = RxState::Receiving;
// Set up the DMA read
self.inner.rxd.ptr.write(|w|
// The PTR field is a full 32 bits wide and accepts the full range
// of values.
unsafe { w.ptr().bits(buf.as_ptr() as u32) });
self.inner.rxd.maxcnt.write(|w|
// We're giving it the length of the buffer, so no danger of
// accessing invalid memory. We have verified that the length of the
// buffer fits in an `u8`, so the cast to `u8` is also fine.
//
// The MAXCNT field is at least 8 bits wide and accepts the full
// range of values.
unsafe { w.maxcnt().bits(buf.len() as _) });
trace!(" irq_rx: buf {:?} {:?}", buf.as_ptr() as u32, buf.len());
// Enable RXRDY interrupt.
self.inner.events_rxdrdy.reset();
self.inner.intenset.write(|w| w.rxdrdy().set());
// Start UARTE Receive transaction
self.inner.tasks_startrx.write(|w|
// `1` is a valid value to write to task registers.
unsafe { w.bits(1) });
}
}
RxState::Receiving => {
trace!(" irq_rx: in state receiving");
if self.inner.events_rxdrdy.read().bits() != 0 {
trace!(" irq_rx: rxdrdy");
// Disable the RXRDY event interrupt
// RXRDY is triggered for every byte, but we only care about whether we have
// some bytes or not. So as soon as we have at least one, disable it, to avoid
// wasting CPU cycles in interrupts.
self.inner.intenclr.write(|w| w.rxdrdy().clear());
self.inner.events_rxdrdy.reset();
self.rx_waker.wake();
self.rx_state = RxState::ReceivingReady;
more_work = true; // in case we also have endrx pending
}
}
RxState::ReceivingReady | RxState::Stopping => {
trace!(" irq_rx: in state ReceivingReady");
if self.inner.events_rxdrdy.read().bits() != 0 {
trace!(" irq_rx: rxdrdy");
self.inner.events_rxdrdy.reset();
}
if self.inner.events_endrx.read().bits() != 0 {
let n: usize = self.inner.rxd.amount.read().amount().bits() as usize;
trace!(" irq_rx: endrx {:?}", n);
self.rx.push(n);
self.inner.events_endrx.reset();
self.rx_waker.wake();
self.rx_state = RxState::Idle;
more_work = true; // start another rx if possible
}
}
}
}
more_work = true;
while more_work {
more_work = false;
match self.tx_state {
TxState::Idle => {
trace!(" irq_tx: in state Idle");
let buf = self.tx.pop_buf();
if buf.len() != 0 {
trace!(" irq_tx: starting {:?}", buf.len());
self.tx_state = TxState::Transmitting(buf.len());
// Set up the DMA write
self.inner.txd.ptr.write(|w|
// The PTR field is a full 32 bits wide and accepts the full range
// of values.
unsafe { w.ptr().bits(buf.as_ptr() as u32) });
self.inner.txd.maxcnt.write(|w|
// We're giving it the length of the buffer, so no danger of
// accessing invalid memory. We have verified that the length of the
// buffer fits in an `u8`, so the cast to `u8` is also fine.
//
// The MAXCNT field is 8 bits wide and accepts the full range of
// values.
unsafe { w.maxcnt().bits(buf.len() as _) });
// Start UARTE Transmit transaction
self.inner.tasks_starttx.write(|w|
// `1` is a valid value to write to task registers.
unsafe { w.bits(1) });
}
}
TxState::Transmitting(n) => {
trace!(" irq_tx: in state Transmitting");
if self.inner.events_endtx.read().bits() != 0 {
self.inner.events_endtx.reset();
trace!(" irq_tx: endtx {:?}", n);
self.tx.pop(n);
self.tx_waker.wake();
self.tx_state = TxState::Idle;
more_work = true; // start another tx if possible
}
}
}
}
trace!("irq: end");
}
}
pub struct Pins {
pub rxd: GpioPin<Input<Floating>>,
pub txd: GpioPin<Output<PushPull>>,
pub cts: Option<GpioPin<Input<Floating>>>,
pub rts: Option<GpioPin<Output<PushPull>>>,
}
mod private {
use nrf52840_pac::{UARTE0, UARTE1};
pub trait Sealed {}
impl Sealed for UARTE0 {}
impl Sealed for UARTE1 {}
}
pub trait Instance: Deref<Target = uarte0::RegisterBlock> + Sized + private::Sealed {
fn interrupt() -> Interrupt;
#[doc(hidden)]
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self>;
#[doc(hidden)]
fn set_state(_cs: &CriticalSection, state: *mut UarteState<Self>);
}
#[interrupt]
unsafe fn UARTE0_UART0() {
interrupt::free(|cs| UARTE0::get_state(cs).as_mut().unwrap().on_interrupt());
}
#[interrupt]
unsafe fn UARTE1() {
interrupt::free(|cs| UARTE1::get_state(cs).as_mut().unwrap().on_interrupt());
}
static mut UARTE0_STATE: *mut UarteState<UARTE0> = ptr::null_mut();
static mut UARTE1_STATE: *mut UarteState<UARTE1> = ptr::null_mut();
impl Instance for UARTE0 {
fn interrupt() -> Interrupt {
Interrupt::UARTE0_UART0
}
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self> {
unsafe { UARTE0_STATE } // Safe because of CriticalSection
}
fn set_state(_cs: &CriticalSection, state: *mut UarteState<Self>) {
unsafe { UARTE0_STATE = state } // Safe because of CriticalSection
}
}
impl Instance for UARTE1 {
fn interrupt() -> Interrupt {
Interrupt::UARTE1
}
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self> {
unsafe { UARTE1_STATE } // Safe because of CriticalSection
}
fn set_state(_cs: &CriticalSection, state: *mut UarteState<Self>) {
unsafe { UARTE1_STATE = state } // Safe because of CriticalSection
}
}