Merge #914
914: (embassy-rp): Add I2C master implementation r=Dirbaio a=MathiasKoch
This PR adds both blocking and DMA based async implementations of I2C master.
Both E-H 0.2 & E-H 1.0 abstractions are implemented as well.
### Questions & concerns:
- Do we need an I2C interrupt handler (for transfer done, abort & error handling?) (async only)
- Do we need to add some automatic attempt at unblocking an I2C bus in case of failures (see ref: 7ebfd553f3/src/i2c_dma.c (L116-L142))
- Should I add `vectored_{read, write}` implementations?
Co-authored-by: Mathias <mk@blackbird.online>
Co-authored-by: Mathias Koch <mk@blackbird.online>
This commit is contained in:
bors[bot]
GitHub
commit
9bb43ffe9a
556
embassy-rp/src/i2c.rs
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556
embassy-rp/src/i2c.rs
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@ -0,0 +1,556 @@
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use core::marker::PhantomData;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use pac::i2c;
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use crate::dma::AnyChannel;
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use crate::gpio::sealed::Pin;
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use crate::gpio::AnyPin;
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use crate::{pac, peripherals, Peripheral};
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/// I2C error abort reason
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum AbortReason {
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/// A bus operation was not acknowledged, e.g. due to the addressed device
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/// not being available on the bus or the device not being ready to process
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/// requests at the moment
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NoAcknowledge,
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/// The arbitration was lost, e.g. electrical problems with the clock signal
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ArbitrationLoss,
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Other(u32),
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}
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/// I2C error
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// I2C abort with error
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Abort(AbortReason),
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/// User passed in a read buffer that was 0 length
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InvalidReadBufferLength,
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/// User passed in a write buffer that was 0 length
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InvalidWriteBufferLength,
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/// Target i2c address is out of range
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AddressOutOfRange(u16),
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/// Target i2c address is reserved
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AddressReserved(u16),
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}
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#[non_exhaustive]
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#[derive(Copy, Clone)]
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pub struct Config {
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pub frequency: u32,
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}
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impl Default for Config {
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fn default() -> Self {
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Self { frequency: 100_000 }
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}
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}
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const FIFO_SIZE: u8 = 16;
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pub struct I2c<'d, T: Instance, M: Mode> {
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_tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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_rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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_dma_buf: [u16; 256],
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phantom: PhantomData<(&'d mut T, M)>,
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}
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impl<'d, T: Instance> I2c<'d, T, Blocking> {
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pub fn new_blocking(
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(scl, sda);
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Self::new_inner(_peri, scl.map_into(), sda.map_into(), None, None, config)
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}
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}
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impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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fn new_inner(
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_peri: impl Peripheral<P = T> + 'd,
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scl: PeripheralRef<'d, AnyPin>,
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sda: PeripheralRef<'d, AnyPin>,
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_tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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_rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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config: Config,
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) -> Self {
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into_ref!(_peri);
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assert!(config.frequency <= 1_000_000);
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assert!(config.frequency > 0);
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let p = T::regs();
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unsafe {
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p.ic_enable().write(|w| w.set_enable(false));
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// Select controller mode & speed
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p.ic_con().modify(|w| {
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// Always use "fast" mode (<= 400 kHz, works fine for standard
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// mode too)
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w.set_speed(i2c::vals::Speed::FAST);
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w.set_master_mode(true);
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w.set_ic_slave_disable(true);
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w.set_ic_restart_en(true);
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w.set_tx_empty_ctrl(true);
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});
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// Set FIFO watermarks to 1 to make things simpler. This is encoded
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// by a register value of 0.
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p.ic_tx_tl().write(|w| w.set_tx_tl(0));
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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// Configure SCL & SDA pins
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scl.io().ctrl().write(|w| w.set_funcsel(3));
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sda.io().ctrl().write(|w| w.set_funcsel(3));
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scl.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_ie(true);
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w.set_od(false);
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w.set_pue(true);
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w.set_pde(false);
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});
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sda.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_ie(true);
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w.set_od(false);
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w.set_pue(true);
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w.set_pde(false);
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});
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// Configure baudrate
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// There are some subtleties to I2C timing which we are completely
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// ignoring here See:
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// https://github.com/raspberrypi/pico-sdk/blob/bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7/src/rp2_common/hardware_i2c/i2c.c#L69
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let clk_base = crate::clocks::clk_peri_freq();
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let period = (clk_base + config.frequency / 2) / config.frequency;
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let lcnt = period * 3 / 5; // spend 3/5 (60%) of the period low
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let hcnt = period - lcnt; // and 2/5 (40%) of the period high
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// Check for out-of-range divisors:
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assert!(hcnt <= 0xffff);
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assert!(lcnt <= 0xffff);
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assert!(hcnt >= 8);
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assert!(lcnt >= 8);
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// Per I2C-bus specification a device in standard or fast mode must
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// internally provide a hold time of at least 300ns for the SDA
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// signal to bridge the undefined region of the falling edge of SCL.
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// A smaller hold time of 120ns is used for fast mode plus.
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let sda_tx_hold_count = if config.frequency < 1_000_000 {
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// sda_tx_hold_count = clk_base [cycles/s] * 300ns * (1s /
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// 1e9ns) Reduce 300/1e9 to 3/1e7 to avoid numbers that don't
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// fit in uint. Add 1 to avoid division truncation.
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((clk_base * 3) / 10_000_000) + 1
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} else {
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// fast mode plus requires a clk_base > 32MHz
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assert!(clk_base >= 32_000_000);
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// sda_tx_hold_count = clk_base [cycles/s] * 120ns * (1s /
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// 1e9ns) Reduce 120/1e9 to 3/25e6 to avoid numbers that don't
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// fit in uint. Add 1 to avoid division truncation.
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((clk_base * 3) / 25_000_000) + 1
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};
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assert!(sda_tx_hold_count <= lcnt - 2);
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p.ic_fs_scl_hcnt().write(|w| w.set_ic_fs_scl_hcnt(hcnt as u16));
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p.ic_fs_scl_lcnt().write(|w| w.set_ic_fs_scl_lcnt(lcnt as u16));
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p.ic_fs_spklen()
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.write(|w| w.set_ic_fs_spklen(if lcnt < 16 { 1 } else { (lcnt / 16) as u8 }));
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p.ic_sda_hold()
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.modify(|w| w.set_ic_sda_tx_hold(sda_tx_hold_count as u16));
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// Enable I2C block
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p.ic_enable().write(|w| w.set_enable(true));
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}
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Self {
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_tx_dma,
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_rx_dma,
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_dma_buf: [0; 256],
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phantom: PhantomData,
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}
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}
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fn setup(addr: u16) -> Result<(), Error> {
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if addr >= 0x80 {
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return Err(Error::AddressOutOfRange(addr));
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}
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if i2c_reserved_addr(addr) {
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return Err(Error::AddressReserved(addr));
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}
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let p = T::regs();
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unsafe {
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p.ic_enable().write(|w| w.set_enable(false));
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p.ic_tar().write(|w| w.set_ic_tar(addr));
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p.ic_enable().write(|w| w.set_enable(true));
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}
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Ok(())
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}
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fn read_and_clear_abort_reason(&mut self) -> Result<(), Error> {
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let p = T::regs();
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unsafe {
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let abort_reason = p.ic_tx_abrt_source().read();
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if abort_reason.0 != 0 {
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// Note clearing the abort flag also clears the reason, and this
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// instance of flag is clear-on-read! Note also the
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// IC_CLR_TX_ABRT register always reads as 0.
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p.ic_clr_tx_abrt().read();
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let reason = if abort_reason.abrt_7b_addr_noack()
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| abort_reason.abrt_10addr1_noack()
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| abort_reason.abrt_10addr2_noack()
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{
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AbortReason::NoAcknowledge
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} else if abort_reason.arb_lost() {
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AbortReason::ArbitrationLoss
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} else {
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AbortReason::Other(abort_reason.0)
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};
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Err(Error::Abort(reason))
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} else {
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Ok(())
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}
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}
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}
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fn read_blocking_internal(&mut self, buffer: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
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if buffer.is_empty() {
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return Err(Error::InvalidReadBufferLength);
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}
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let p = T::regs();
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let lastindex = buffer.len() - 1;
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for (i, byte) in buffer.iter_mut().enumerate() {
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let first = i == 0;
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let last = i == lastindex;
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// NOTE(unsafe) We have &mut self
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unsafe {
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// wait until there is space in the FIFO to write the next byte
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while p.ic_txflr().read().txflr() == FIFO_SIZE {}
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p.ic_data_cmd().write(|w| {
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w.set_restart(restart && first);
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w.set_stop(send_stop && last);
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w.set_cmd(true);
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});
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while p.ic_rxflr().read().rxflr() == 0 {
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self.read_and_clear_abort_reason()?;
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}
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*byte = p.ic_data_cmd().read().dat();
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}
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}
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Ok(())
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}
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fn write_blocking_internal(&mut self, bytes: &[u8], send_stop: bool) -> Result<(), Error> {
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if bytes.is_empty() {
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return Err(Error::InvalidWriteBufferLength);
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}
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let p = T::regs();
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for (i, byte) in bytes.iter().enumerate() {
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let last = i == bytes.len() - 1;
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// NOTE(unsafe) We have &mut self
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unsafe {
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p.ic_data_cmd().write(|w| {
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w.set_stop(send_stop && last);
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w.set_dat(*byte);
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});
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// Wait until the transmission of the address/data from the
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// internal shift register has completed. For this to function
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// correctly, the TX_EMPTY_CTRL flag in IC_CON must be set. The
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// TX_EMPTY_CTRL flag was set in i2c_init.
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while !p.ic_raw_intr_stat().read().tx_empty() {}
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let abort_reason = self.read_and_clear_abort_reason();
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if abort_reason.is_err() || (send_stop && last) {
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// If the transaction was aborted or if it completed
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// successfully wait until the STOP condition has occured.
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while !p.ic_raw_intr_stat().read().stop_det() {}
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p.ic_clr_stop_det().read().clr_stop_det();
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}
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// Note the hardware issues a STOP automatically on an abort
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// condition. Note also the hardware clears RX FIFO as well as
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// TX on abort, ecause we set hwparam
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// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
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abort_reason?;
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}
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}
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Ok(())
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}
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// =========================
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// Blocking public API
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// =========================
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pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.read_blocking_internal(buffer, true, true)
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// Automatic Stop
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}
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pub fn blocking_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.write_blocking_internal(bytes, true)
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}
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pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.write_blocking_internal(bytes, false)?;
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self.read_blocking_internal(buffer, true, true)
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// Automatic Stop
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}
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}
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mod eh02 {
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use super::*;
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impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> {
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type Error = Error;
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fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_read(address, buffer)
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}
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}
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impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> {
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type Error = Error;
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fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(address, bytes)
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}
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}
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impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> {
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type Error = Error;
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fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_write_read(address, bytes, buffer)
|
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}
|
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}
|
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}
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#[cfg(feature = "unstable-traits")]
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mod eh1 {
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use super::*;
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impl embedded_hal_1::i2c::Error for Error {
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fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
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match *self {
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Self::Abort(AbortReason::ArbitrationLoss) => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
|
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Self::Abort(AbortReason::NoAcknowledge) => {
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embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address)
|
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}
|
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Self::Abort(AbortReason::Other(_)) => embedded_hal_1::i2c::ErrorKind::Other,
|
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Self::InvalidReadBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
|
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Self::InvalidWriteBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
|
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Self::AddressOutOfRange(_) => embedded_hal_1::i2c::ErrorKind::Other,
|
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Self::AddressReserved(_) => embedded_hal_1::i2c::ErrorKind::Other,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, T, M> {
|
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type Error = Error;
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::blocking::I2c for I2c<'d, T, M> {
|
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fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
||||
self.blocking_read(address, buffer)
|
||||
}
|
||||
|
||||
fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Self::Error> {
|
||||
self.blocking_write(address, buffer)
|
||||
}
|
||||
|
||||
fn write_iter<B>(&mut self, address: u8, bytes: B) -> Result<(), Self::Error>
|
||||
where
|
||||
B: IntoIterator<Item = u8>,
|
||||
{
|
||||
let mut peekable = bytes.into_iter().peekable();
|
||||
Self::setup(address.into())?;
|
||||
|
||||
while let Some(tx) = peekable.next() {
|
||||
self.write_blocking_internal(&[tx], peekable.peek().is_none())?;
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn write_iter_read<B>(&mut self, address: u8, bytes: B, buffer: &mut [u8]) -> Result<(), Self::Error>
|
||||
where
|
||||
B: IntoIterator<Item = u8>,
|
||||
{
|
||||
let peekable = bytes.into_iter().peekable();
|
||||
Self::setup(address.into())?;
|
||||
|
||||
for tx in peekable {
|
||||
self.write_blocking_internal(&[tx], false)?
|
||||
}
|
||||
self.read_blocking_internal(buffer, true, true)
|
||||
}
|
||||
|
||||
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
|
||||
self.blocking_write_read(address, wr_buffer, rd_buffer)
|
||||
}
|
||||
|
||||
fn transaction<'a>(
|
||||
&mut self,
|
||||
address: u8,
|
||||
operations: &mut [embedded_hal_1::i2c::blocking::Operation<'a>],
|
||||
) -> Result<(), Self::Error> {
|
||||
Self::setup(address.into())?;
|
||||
for i in 0..operations.len() {
|
||||
let last = i == operations.len() - 1;
|
||||
match &mut operations[i] {
|
||||
embedded_hal_1::i2c::blocking::Operation::Read(buf) => {
|
||||
self.read_blocking_internal(buf, false, last)?
|
||||
}
|
||||
embedded_hal_1::i2c::blocking::Operation::Write(buf) => self.write_blocking_internal(buf, last)?,
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn transaction_iter<'a, O>(&mut self, address: u8, operations: O) -> Result<(), Self::Error>
|
||||
where
|
||||
O: IntoIterator<Item = embedded_hal_1::i2c::blocking::Operation<'a>>,
|
||||
{
|
||||
Self::setup(address.into())?;
|
||||
let mut peekable = operations.into_iter().peekable();
|
||||
while let Some(operation) = peekable.next() {
|
||||
let last = peekable.peek().is_none();
|
||||
match operation {
|
||||
embedded_hal_1::i2c::blocking::Operation::Read(buf) => {
|
||||
self.read_blocking_internal(buf, false, last)?
|
||||
}
|
||||
embedded_hal_1::i2c::blocking::Operation::Write(buf) => self.write_blocking_internal(buf, last)?,
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn i2c_reserved_addr(addr: u16) -> bool {
|
||||
(addr & 0x78) == 0 || (addr & 0x78) == 0x78
|
||||
}
|
||||
|
||||
mod sealed {
|
||||
use embassy_cortex_m::interrupt::Interrupt;
|
||||
|
||||
pub trait Instance {
|
||||
const TX_DREQ: u8;
|
||||
const RX_DREQ: u8;
|
||||
|
||||
type Interrupt: Interrupt;
|
||||
|
||||
fn regs() -> crate::pac::i2c::I2c;
|
||||
}
|
||||
|
||||
pub trait Mode {}
|
||||
|
||||
pub trait SdaPin<T: Instance> {}
|
||||
pub trait SclPin<T: Instance> {}
|
||||
}
|
||||
|
||||
pub trait Mode: sealed::Mode {}
|
||||
|
||||
macro_rules! impl_mode {
|
||||
($name:ident) => {
|
||||
impl sealed::Mode for $name {}
|
||||
impl Mode for $name {}
|
||||
};
|
||||
}
|
||||
|
||||
pub struct Blocking;
|
||||
pub struct Async;
|
||||
|
||||
impl_mode!(Blocking);
|
||||
impl_mode!(Async);
|
||||
|
||||
pub trait Instance: sealed::Instance {}
|
||||
|
||||
macro_rules! impl_instance {
|
||||
($type:ident, $irq:ident, $tx_dreq:expr, $rx_dreq:expr) => {
|
||||
impl sealed::Instance for peripherals::$type {
|
||||
const TX_DREQ: u8 = $tx_dreq;
|
||||
const RX_DREQ: u8 = $rx_dreq;
|
||||
|
||||
type Interrupt = crate::interrupt::$irq;
|
||||
|
||||
fn regs() -> pac::i2c::I2c {
|
||||
pac::$type
|
||||
}
|
||||
}
|
||||
impl Instance for peripherals::$type {}
|
||||
};
|
||||
}
|
||||
|
||||
impl_instance!(I2C0, I2C0_IRQ, 32, 33);
|
||||
impl_instance!(I2C1, I2C1_IRQ, 34, 35);
|
||||
|
||||
pub trait SdaPin<T: Instance>: sealed::SdaPin<T> + crate::gpio::Pin {}
|
||||
pub trait SclPin<T: Instance>: sealed::SclPin<T> + crate::gpio::Pin {}
|
||||
|
||||
macro_rules! impl_pin {
|
||||
($pin:ident, $instance:ident, $function:ident) => {
|
||||
impl sealed::$function<peripherals::$instance> for peripherals::$pin {}
|
||||
impl $function<peripherals::$instance> for peripherals::$pin {}
|
||||
};
|
||||
}
|
||||
|
||||
impl_pin!(PIN_0, I2C0, SdaPin);
|
||||
impl_pin!(PIN_1, I2C0, SclPin);
|
||||
impl_pin!(PIN_2, I2C1, SdaPin);
|
||||
impl_pin!(PIN_3, I2C1, SclPin);
|
||||
impl_pin!(PIN_4, I2C0, SdaPin);
|
||||
impl_pin!(PIN_5, I2C0, SclPin);
|
||||
impl_pin!(PIN_6, I2C1, SdaPin);
|
||||
impl_pin!(PIN_7, I2C1, SclPin);
|
||||
impl_pin!(PIN_8, I2C0, SdaPin);
|
||||
impl_pin!(PIN_9, I2C0, SclPin);
|
||||
impl_pin!(PIN_10, I2C1, SdaPin);
|
||||
impl_pin!(PIN_11, I2C1, SclPin);
|
||||
impl_pin!(PIN_12, I2C0, SdaPin);
|
||||
impl_pin!(PIN_13, I2C0, SclPin);
|
||||
impl_pin!(PIN_14, I2C1, SdaPin);
|
||||
impl_pin!(PIN_15, I2C1, SclPin);
|
||||
impl_pin!(PIN_16, I2C0, SdaPin);
|
||||
impl_pin!(PIN_17, I2C0, SclPin);
|
||||
impl_pin!(PIN_18, I2C1, SdaPin);
|
||||
impl_pin!(PIN_19, I2C1, SclPin);
|
||||
impl_pin!(PIN_20, I2C0, SdaPin);
|
||||
impl_pin!(PIN_21, I2C0, SclPin);
|
||||
impl_pin!(PIN_22, I2C1, SdaPin);
|
||||
impl_pin!(PIN_23, I2C1, SclPin);
|
||||
impl_pin!(PIN_24, I2C0, SdaPin);
|
||||
impl_pin!(PIN_25, I2C0, SclPin);
|
||||
impl_pin!(PIN_26, I2C1, SdaPin);
|
||||
impl_pin!(PIN_27, I2C1, SclPin);
|
||||
impl_pin!(PIN_28, I2C0, SdaPin);
|
||||
impl_pin!(PIN_29, I2C0, SclPin);
|
||||
@ -8,6 +8,7 @@ mod intrinsics;
|
||||
|
||||
pub mod dma;
|
||||
pub mod gpio;
|
||||
pub mod i2c;
|
||||
pub mod interrupt;
|
||||
pub mod rom_data;
|
||||
pub mod rtc;
|
||||
@ -75,6 +76,9 @@ embassy_hal_common::peripherals! {
|
||||
SPI0,
|
||||
SPI1,
|
||||
|
||||
I2C0,
|
||||
I2C1,
|
||||
|
||||
DMA_CH0,
|
||||
DMA_CH1,
|
||||
DMA_CH2,
|
||||
|
||||
@ -428,9 +428,11 @@ mod eh02 {
|
||||
|
||||
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for UartTx<'d, T, M> {
|
||||
type Error = Error;
|
||||
|
||||
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
||||
self.blocking_write(buffer)
|
||||
}
|
||||
|
||||
fn bflush(&mut self) -> Result<(), Self::Error> {
|
||||
self.blocking_flush()
|
||||
}
|
||||
@ -438,6 +440,7 @@ mod eh02 {
|
||||
|
||||
impl<'d, T: Instance, M: Mode> embedded_hal_02::serial::Read<u8> for Uart<'d, T, M> {
|
||||
type Error = Error;
|
||||
|
||||
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
||||
embedded_hal_02::serial::Read::read(&mut self.rx)
|
||||
}
|
||||
@ -445,9 +448,11 @@ mod eh02 {
|
||||
|
||||
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for Uart<'d, T, M> {
|
||||
type Error = Error;
|
||||
|
||||
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
||||
self.blocking_write(buffer)
|
||||
}
|
||||
|
||||
fn bflush(&mut self) -> Result<(), Self::Error> {
|
||||
self.blocking_flush()
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user