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Merge pull request #305 from bobmcwhirter/spi_dma_take3

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Spi dma take3
This commit is contained in:
Dario Nieuwenhuis 2021-07-24 09:24:11 +02:00 committed by GitHub
commit 9c503a9256
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GPG Key ID: 4AEE18F83AFDEB23
16 changed files with 1235 additions and 57 deletions
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23
embassy-nrf/src/spim.rs
View File

@ -9,7 +9,7 @@ use embassy::traits;
use embassy::util::{AtomicWaker, Unborrow};
use embassy_extras::unborrow;
use futures::future::poll_fn;
use traits::spi::FullDuplex;
use traits::spi::{FullDuplex, Read, Spi, Write};
use crate::gpio;
use crate::gpio::sealed::Pin as _;
@ -177,22 +177,31 @@ impl<'d, T: Instance> Drop for Spim<'d, T> {
}
}
impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
impl<'d, T: Instance> Spi<u8> for Spim<'d, T> {
type Error = Error;
}
impl<'d, T: Instance> Read<u8> for Spim<'d, T> {
#[rustfmt::skip]
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
#[rustfmt::skip]
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
#[rustfmt::skip]
type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
type ReadFuture<'a> where Self: 'a = impl Future<Output=Result<(), Self::Error>> + 'a;
fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
self.read_write(data, &[])
}
}
impl<'d, T: Instance> Write<u8> for Spim<'d, T> {
#[rustfmt::skip]
type WriteFuture<'a> where Self: 'a = impl Future<Output=Result<(), Self::Error>> + 'a;
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
self.read_write(&mut [], data)
}
}
impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
#[rustfmt::skip]
type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn read_write<'a>(&'a mut self, rx: &'a mut [u8], tx: &'a [u8]) -> Self::WriteReadFuture<'a> {
async move {

33
embassy-stm32/src/dma/bdma.rs
View File

@ -47,6 +47,7 @@ pub(crate) unsafe fn do_transfer(
peri_addr: *const u8,
mem_addr: *mut u8,
mem_len: usize,
incr_mem: bool,
#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
#[cfg(dmamux)] dmamux_ch_num: u8,
) -> impl Future<Output = ()> {
@ -88,7 +89,11 @@ pub(crate) unsafe fn do_transfer(
ch.cr().write(|w| {
w.set_psize(vals::Size::BITS8);
w.set_msize(vals::Size::BITS8);
if incr_mem {
w.set_minc(vals::Inc::ENABLED);
} else {
w.set_minc(vals::Inc::DISABLED);
}
w.set_dir(dir);
w.set_teie(true);
w.set_tcie(true);
@ -182,6 +187,7 @@ pac::dma_channels! {
src,
buf.as_mut_ptr(),
buf.len(),
true,
#[cfg(dmamux)]
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
#[cfg(dmamux)]
@ -206,6 +212,33 @@ pac::dma_channels! {
dst,
buf.as_ptr() as *mut u8,
buf.len(),
true,
#[cfg(dmamux)]
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
#[cfg(dmamux)]
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
)
}
}
fn write_x<'a>(
&'a mut self,
request: Request,
word: &u8,
count: usize,
dst: *mut u8,
) -> Self::WriteFuture<'a> {
unsafe {
do_transfer(
crate::pac::$dma_peri,
$channel_num,
(dma_num!($dma_peri) * 8) + $channel_num,
request,
vals::Dir::FROMMEMORY,
dst,
word as *const u8 as *mut u8,
count,
false,
#[cfg(dmamux)]
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
#[cfg(dmamux)]

38
embassy-stm32/src/dma/dma.rs
View File

@ -48,6 +48,7 @@ pub(crate) unsafe fn do_transfer(
peri_addr: *const u8,
mem_addr: *mut u8,
mem_len: usize,
incr_mem: bool,
#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
#[cfg(dmamux)] dmamux_ch_num: u8,
) -> impl Future<Output = ()> {
@ -87,22 +88,27 @@ pub(crate) unsafe fn do_transfer(
w.set_dir(dir);
w.set_msize(vals::Size::BITS8);
w.set_psize(vals::Size::BITS8);
if incr_mem {
w.set_minc(vals::Inc::INCREMENTED);
} else {
w.set_minc(vals::Inc::FIXED);
}
w.set_pinc(vals::Inc::FIXED);
w.set_teie(true);
w.set_tcie(true);
#[cfg(dma_v1)]
w.set_trbuff(true);
w.set_en(true);
#[cfg(dma_v2)]
w.set_chsel(request);
w.set_en(true);
});
}
async move {
let res = poll_fn(|cx| {
let n = channel_number as usize;
let n = state_number as usize;
STATE.ch_wakers[n].register(cx.waker());
match STATE.ch_status[n].load(Ordering::Acquire) {
CH_STATUS_NONE => Poll::Pending,
@ -187,6 +193,7 @@ pac::dma_channels! {
src,
buf.as_mut_ptr(),
buf.len(),
true,
#[cfg(dmamux)]
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
#[cfg(dmamux)]
@ -211,6 +218,33 @@ pac::dma_channels! {
dst,
buf.as_ptr() as *mut u8,
buf.len(),
true,
#[cfg(dmamux)]
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
#[cfg(dmamux)]
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
)
}
}
fn write_x<'a>(
&'a mut self,
request: Request,
word: &u8,
num: usize,
dst: *mut u8,
) -> Self::WriteFuture<'a> {
unsafe {
do_transfer(
crate::pac::$dma_peri,
$channel_num,
(dma_num!($dma_peri) * 8) + $channel_num,
request,
vals::Dir::MEMORYTOPERIPHERAL,
dst,
word as *const u8 as *mut u8,
num,
false,
#[cfg(dmamux)]
<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
#[cfg(dmamux)]

8
embassy-stm32/src/dma/mod.rs
View File

@ -42,6 +42,14 @@ pub trait Channel: sealed::Channel {
buf: &'a [u8],
dst: *mut u8,
) -> Self::WriteFuture<'a>;
fn write_x<'a>(
&'a mut self,
request: Request,
word: &u8,
num: usize,
dst: *mut u8,
) -> Self::WriteFuture<'a>;
}
pub struct NoDma;

59
embassy-stm32/src/spi/mod.rs
View File

@ -4,7 +4,7 @@
#[cfg_attr(spi_v2, path = "v2.rs")]
#[cfg_attr(spi_v3, path = "v3.rs")]
mod _version;
use crate::{peripherals, rcc::RccPeripheral};
use crate::{dma, peripherals, rcc::RccPeripheral};
pub use _version::*;
use crate::gpio::Pin;
@ -62,15 +62,22 @@ pub(crate) mod sealed {
pub trait MisoPin<T: Instance>: Pin {
fn af_num(&self) -> u8;
}
pub trait TxDmaChannel<T: Instance> {
fn request(&self) -> dma::Request;
}
pub trait RxDmaChannel<T: Instance> {
fn request(&self) -> dma::Request;
}
}
pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
pub trait SckPin<T: Instance>: sealed::SckPin<T> + 'static {}
pub trait MosiPin<T: Instance>: sealed::MosiPin<T> + 'static {}
pub trait MisoPin<T: Instance>: sealed::MisoPin<T> + 'static {}
pub trait Instance: sealed::Instance + RccPeripheral {}
pub trait SckPin<T: Instance>: sealed::SckPin<T> {}
pub trait MosiPin<T: Instance>: sealed::MosiPin<T> {}
pub trait MisoPin<T: Instance>: sealed::MisoPin<T> {}
pub trait TxDmaChannel<T: Instance>: sealed::TxDmaChannel<T> + dma::Channel {}
pub trait RxDmaChannel<T: Instance>: sealed::RxDmaChannel<T> + dma::Channel {}
crate::pac::peripherals!(
(spi, $inst:ident) => {
@ -109,3 +116,39 @@ crate::pac::peripheral_pins!(
impl_pin!($inst, $pin, MisoPin, $af);
};
);
macro_rules! impl_dma {
($inst:ident, {dmamux: $dmamux:ident}, $signal:ident, $request:expr) => {
impl<T> sealed::$signal<peripherals::$inst> for T
where
T: crate::dma::MuxChannel<Mux = crate::dma::$dmamux>,
{
fn request(&self) -> dma::Request {
$request
}
}
impl<T> $signal<peripherals::$inst> for T where
T: crate::dma::MuxChannel<Mux = crate::dma::$dmamux>
{
}
};
($inst:ident, {channel: $channel:ident}, $signal:ident, $request:expr) => {
impl sealed::$signal<peripherals::$inst> for peripherals::$channel {
fn request(&self) -> dma::Request {
$request
}
}
impl $signal<peripherals::$inst> for peripherals::$channel {}
};
}
crate::pac::peripheral_dma_channels! {
($peri:ident, spi, $kind:ident, RX, $channel:tt, $request:expr) => {
impl_dma!($peri, $channel, RxDmaChannel, $request);
};
($peri:ident, spi, $kind:ident, TX, $channel:tt, $request:expr) => {
impl_dma!($peri, $channel, TxDmaChannel, $request);
};
}

212
embassy-stm32/src/spi/v1.rs
View File

@ -1,14 +1,21 @@
#![macro_use]
use crate::dma::NoDma;
use crate::gpio::{sealed::Pin, AnyPin};
use crate::pac::spi;
use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
use crate::spi::{
ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
WordSize,
};
use crate::time::Hertz;
use core::future::Future;
use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow;
use embassy_extras::unborrow;
use embassy_traits::spi as traits;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::join3;
impl WordSize {
fn dff(&self) -> spi::vals::Dff {
@ -19,27 +26,31 @@ impl WordSize {
}
}
pub struct Spi<'d, T: Instance> {
pub struct Spi<'d, T: Instance, Tx, Rx> {
sck: AnyPin,
mosi: AnyPin,
miso: AnyPin,
txdma: Tx,
rxdma: Rx,
current_word_size: WordSize,
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: Instance> Spi<'d, T> {
impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn new<F>(
_peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target = impl MisoPin<T>>,
txdma: impl Unborrow<Target = Tx>,
rxdma: impl Unborrow<Target = Rx>,
freq: F,
config: Config,
) -> Self
where
F: Into<Hertz>,
{
unborrow!(sck, mosi, miso);
unborrow!(sck, mosi, miso, txdma, rxdma);
unsafe {
sck.set_as_af(sck.af_num());
@ -94,6 +105,8 @@ impl<'d, T: Instance> Spi<'d, T> {
sck,
mosi,
miso,
txdma,
rxdma,
current_word_size: WordSize::EightBit,
phantom: PhantomData,
}
@ -128,9 +141,151 @@ impl<'d, T: Instance> Spi<'d, T> {
self.current_word_size = word_size;
}
}
#[allow(unused)]
async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
{
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
self.set_word_size(WordSize::EightBit);
let request = self.txdma.request();
let dst = T::regs().dr().ptr() as *mut u8;
let f = self.txdma.write(request, write, dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
f.await;
Ok(())
}
#[allow(unused)]
async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true);
});
}
self.set_word_size(WordSize::EightBit);
let clock_byte_count = read.len();
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;
let clock_byte = 0x00;
let tx_f = self
.txdma
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
join3(tx_f, rx_f, Self::wait_for_idle()).await;
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
#[allow(unused)]
async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
assert!(read.len() >= write.len());
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true);
});
}
self.set_word_size(WordSize::EightBit);
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;
let tx_f = self.txdma.write(tx_request, write, tx_dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
join3(tx_f, rx_f, Self::wait_for_idle()).await;
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
async fn wait_for_idle() {
unsafe {
while T::regs().sr().read().bsy() {
// spin
}
}
}
}
impl<'d, T: Instance> Drop for Spi<'d, T> {
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
fn drop(&mut self) {
unsafe {
self.sck.set_as_analog();
@ -140,7 +295,7 @@ impl<'d, T: Instance> Drop for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
@ -176,7 +331,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
@ -217,7 +372,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
@ -253,7 +408,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
@ -291,3 +446,42 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
Ok(words)
}
}
impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
type Error = super::Error;
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> {
#[rustfmt::skip]
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
self.write_dma_u8(data)
}
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::Read<u8>
for Spi<'d, T, Tx, Rx>
{
#[rustfmt::skip]
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
self.read_dma_u8(data)
}
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::FullDuplex<u8>
for Spi<'d, T, Tx, Rx>
{
#[rustfmt::skip]
type WriteReadFuture<'a> where Self: 'a = impl Future<Output=Result<(), Self::Error>> + 'a;
fn read_write<'a>(
&'a mut self,
read: &'a mut [u8],
write: &'a [u8],
) -> Self::WriteReadFuture<'a> {
self.read_write_dma_u8(read, write)
}
}

218
embassy-stm32/src/spi/v2.rs
View File

@ -1,16 +1,23 @@
#![macro_use]
use crate::dma::NoDma;
use crate::gpio::{AnyPin, Pin};
use crate::pac::gpio::vals::{Afr, Moder};
use crate::pac::gpio::Gpio;
use crate::pac::spi;
use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
use crate::spi::{
ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
WordSize,
};
use crate::time::Hertz;
use core::future::Future;
use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow;
use embassy_extras::unborrow;
use embassy_traits::spi as traits;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::join3;
impl WordSize {
fn ds(&self) -> spi::vals::Ds {
@ -28,26 +35,30 @@ impl WordSize {
}
}
pub struct Spi<'d, T: Instance> {
pub struct Spi<'d, T: Instance, Tx, Rx> {
sck: AnyPin,
mosi: AnyPin,
miso: AnyPin,
txdma: Tx,
rxdma: Rx,
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: Instance> Spi<'d, T> {
impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn new<F>(
_peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target = impl MisoPin<T>>,
txdma: impl Unborrow<Target = Tx>,
rxdma: impl Unborrow<Target = Rx>,
freq: F,
config: Config,
) -> Self
where
F: Into<Hertz>,
{
unborrow!(sck, mosi, miso);
unborrow!(sck, mosi, miso, txdma, rxdma);
unsafe {
Self::configure_pin(sck.block(), sck.pin() as _, sck.af_num());
@ -98,6 +109,8 @@ impl<'d, T: Instance> Spi<'d, T> {
sck,
mosi,
miso,
txdma,
rxdma,
phantom: PhantomData,
}
}
@ -140,9 +153,157 @@ impl<'d, T: Instance> Spi<'d, T> {
});
}
}
#[allow(unused)]
async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
{
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Self::set_word_size(WordSize::EightBit);
let request = self.txdma.request();
let dst = T::regs().dr().ptr() as *mut u8;
let f = self.txdma.write(request, write, dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
f.await;
Ok(())
}
#[allow(unused)]
async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true);
});
}
Self::set_word_size(WordSize::EightBit);
let clock_byte_count = read.len();
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;
let clock_byte = 0x00;
let tx_f = self
.txdma
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
join3(tx_f, rx_f, Self::wait_for_idle()).await;
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
#[allow(unused)]
async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
assert!(read.len() >= write.len());
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true);
});
}
Self::set_word_size(WordSize::EightBit);
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;
let tx_f = self.txdma.write(tx_request, write, tx_dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
join3(tx_f, rx_f, Self::wait_for_idle()).await;
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
async fn wait_for_idle() {
unsafe {
while T::regs().sr().read().ftlvl() > 0 {
// spin
}
while T::regs().sr().read().frlvl() > 0 {
// spin
}
while T::regs().sr().read().bsy() {
// spin
}
}
}
}
impl<'d, T: Instance> Drop for Spi<'d, T> {
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
fn drop(&mut self) {
unsafe {
Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _);
@ -200,7 +361,7 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
impl<'d, T: Instance, Rx> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, Rx> {
type Error = Error;
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
@ -216,7 +377,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
@ -232,7 +393,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
impl<'d, T: Instance, Rx> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, Rx> {
type Error = Error;
fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
@ -248,7 +409,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
@ -263,3 +424,42 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
Ok(words)
}
}
impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
type Error = super::Error;
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> {
#[rustfmt::skip]
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
self.write_dma_u8(data)
}
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::Read<u8>
for Spi<'d, T, Tx, Rx>
{
#[rustfmt::skip]
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
self.read_dma_u8(data)
}
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::FullDuplex<u8>
for Spi<'d, T, Tx, Rx>
{
#[rustfmt::skip]
type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn read_write<'a>(
&'a mut self,
read: &'a mut [u8],
write: &'a [u8],
) -> Self::WriteReadFuture<'a> {
self.read_write_dma_u8(read, write)
}
}

232
embassy-stm32/src/spi/v3.rs
View File

@ -1,17 +1,25 @@
#![macro_use]
use crate::dma::NoDma;
use crate::gpio::{AnyPin, Pin};
use crate::pac::gpio::vals::{Afr, Moder};
use crate::pac::gpio::Gpio;
use crate::pac::spi;
use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
use crate::spi::{
ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
WordSize,
};
use crate::time::Hertz;
use core::future::Future;
use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow;
use embassy_extras::unborrow;
use embassy_traits::spi as traits;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::join3;
impl WordSize {
fn dsize(&self) -> u8 {
match self {
@ -28,26 +36,31 @@ impl WordSize {
}
}
pub struct Spi<'d, T: Instance> {
#[allow(unused)]
pub struct Spi<'d, T: Instance, Tx = NoDma, Rx = NoDma> {
sck: AnyPin,
mosi: AnyPin,
miso: AnyPin,
txdma: Tx,
rxdma: Rx,
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: Instance> Spi<'d, T> {
impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn new<F>(
_peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target = impl MisoPin<T>>,
txdma: impl Unborrow<Target = Tx>,
rxdma: impl Unborrow<Target = Rx>,
freq: F,
config: Config,
) -> Self
where
F: Into<Hertz>,
{
unborrow!(sck, mosi, miso);
unborrow!(sck, mosi, miso, txdma, rxdma);
unsafe {
Self::configure_pin(sck.block(), sck.pin() as _, sck.af_num());
@ -97,7 +110,6 @@ impl<'d, T: Instance> Spi<'d, T> {
w.set_crcen(false);
w.set_mbr(spi::vals::Mbr(br));
w.set_dsize(WordSize::EightBit.dsize());
//w.set_fthlv(WordSize::EightBit.frxth());
});
T::regs().cr2().modify(|w| {
w.set_tsize(0);
@ -113,6 +125,8 @@ impl<'d, T: Instance> Spi<'d, T> {
sck,
mosi,
miso,
txdma,
rxdma,
phantom: PhantomData,
}
}
@ -161,9 +175,168 @@ impl<'d, T: Instance> Spi<'d, T> {
});
}
}
#[allow(unused)]
async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
{
Self::set_word_size(WordSize::EightBit);
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
let request = self.txdma.request();
let dst = T::regs().txdr().ptr() as *mut u8;
let f = self.txdma.write(request, write, dst);
unsafe {
T::regs().cfg1().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
}
f.await;
unsafe {
T::regs().cfg1().modify(|reg| {
reg.set_txdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
#[allow(unused)]
async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
Self::set_word_size(WordSize::EightBit);
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cfg1().modify(|reg| {
reg.set_rxdmaen(true);
});
}
let clock_byte_count = read.len();
let rx_request = self.rxdma.request();
let rx_src = T::regs().rxdr().ptr() as *mut u8;
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().txdr().ptr() as *mut u8;
let clock_byte = 0x00;
let tx_f = self
.txdma
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
unsafe {
T::regs().cfg1().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
}
join3(tx_f, rx_f, Self::wait_for_idle()).await;
unsafe {
T::regs().cfg1().modify(|reg| {
reg.set_rxdmaen(false);
reg.set_txdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
#[allow(unused)]
async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
assert!(read.len() >= write.len());
Self::set_word_size(WordSize::EightBit);
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cfg1().modify(|reg| {
reg.set_rxdmaen(true);
});
}
let rx_request = self.rxdma.request();
let rx_src = T::regs().rxdr().ptr() as *mut u8;
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let tx_request = self.txdma.request();
let tx_dst = T::regs().txdr().ptr() as *mut u8;
let tx_f = self.txdma.write(tx_request, write, tx_dst);
unsafe {
T::regs().cfg1().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
}
join3(tx_f, rx_f, Self::wait_for_idle()).await;
unsafe {
T::regs().cfg1().modify(|reg| {
reg.set_rxdmaen(false);
reg.set_txdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
async fn wait_for_idle() {
unsafe {
while !T::regs().sr().read().txc() {
// spin
}
while T::regs().sr().read().rxplvl().0 > 0 {
// spin
}
}
}
}
impl<'d, T: Instance> Drop for Spi<'d, T> {
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
fn drop(&mut self) {
unsafe {
Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _);
@ -173,7 +346,7 @@ impl<'d, T: Instance> Drop for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma> {
type Error = Error;
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
@ -210,7 +383,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
@ -267,7 +440,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma> {
type Error = Error;
fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
@ -304,7 +477,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
@ -357,3 +530,42 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
Ok(words)
}
}
impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
type Error = super::Error;
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> {
#[rustfmt::skip]
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
self.write_dma_u8(data)
}
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::Read<u8>
for Spi<'d, T, Tx, Rx>
{
#[rustfmt::skip]
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
self.read_dma_u8(data)
}
}
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::FullDuplex<u8>
for Spi<'d, T, Tx, Rx>
{
#[rustfmt::skip]
type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
fn read_write<'a>(
&'a mut self,
read: &'a mut [u8],
write: &'a [u8],
) -> Self::WriteReadFuture<'a> {
self.read_write_dma_u8(read, write)
}
}

32
embassy-traits/src/spi.rs
View File

@ -18,25 +18,39 @@ use core::future::Future;
///
/// - Some SPIs can work with 8-bit *and* 16-bit words. You can overload this trait with different
/// `Word` types to allow operation in both modes.
pub trait FullDuplex<Word> {
pub trait Spi<Word> {
/// An enumeration of SPI errors
type Error;
}
type WriteFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a
where
Self: 'a;
type ReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a
where
Self: 'a;
pub trait FullDuplex<Word>: Spi<Word> + Write<Word> + Read<Word> {
type WriteReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a
where
Self: 'a;
fn read<'a>(&'a mut self, data: &'a mut [Word]) -> Self::ReadFuture<'a>;
fn write<'a>(&'a mut self, data: &'a [Word]) -> Self::WriteFuture<'a>;
/// The `read` array must be at least as long as the `write` array,
/// but is guaranteed to only be filled with bytes equal to the
/// length of the `write` array.
fn read_write<'a>(
&'a mut self,
read: &'a mut [Word],
write: &'a [Word],
) -> Self::WriteReadFuture<'a>;
}
pub trait Write<Word>: Spi<Word> {
type WriteFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a
where
Self: 'a;
fn write<'a>(&'a mut self, data: &'a [Word]) -> Self::WriteFuture<'a>;
}
pub trait Read<Word>: Write<Word> {
type ReadFuture<'a>: Future<Output = Result<(), Self::Error>> + 'a
where
Self: 'a;
fn read<'a>(&'a mut self, data: &'a mut [Word]) -> Self::ReadFuture<'a>;
}

3
examples/stm32f4/src/bin/spi.rs
View File

@ -18,6 +18,7 @@ use embassy_stm32::dbgmcu::Dbgmcu;
use embassy_stm32::spi::{Config, Spi};
use embassy_stm32::time::Hertz;
use embedded_hal::blocking::spi::Transfer;
use embassy_stm32::dma::NoDma;
#[entry]
fn main() -> ! {
@ -34,6 +35,8 @@ fn main() -> ! {
p.PC10,
p.PC12,
p.PC11,
NoDma,
NoDma,
Hertz(1_000_000),
Config::default(),
);

85
examples/stm32f4/src/bin/spi_dma.rs Normal file
View File

@ -0,0 +1,85 @@
#![no_std]
#![no_main]
#![feature(trait_alias)]
#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]
#![feature(type_alias_impl_trait)]
#![allow(incomplete_features)]
#[path = "../example_common.rs"]
mod example_common;
use core::fmt::Write;
use cortex_m_rt::entry;
use embassy::executor::Executor;
use embassy::time::Clock;
use embassy::util::Forever;
use example_common::*;
use embassy_traits::spi::FullDuplex;
use heapless::String;
use embassy_stm32::spi::{Spi, Config};
use embassy_stm32::pac;
use embassy_stm32::time::Hertz;
use core::str::from_utf8;
#[embassy::task]
async fn main_task() {
let p = embassy_stm32::init(Default::default());
let mut spi = Spi::new(
p.SPI1,
p.PB3,
p.PB5,
p.PB4,
p.DMA2_CH3,
p.DMA2_CH2,
Hertz(1_000_000),
Config::default(),
);
for n in 0u32.. {
let mut write: String<128> = String::new();
let mut read = [0;128];
core::write!(&mut write, "Hello DMA World {}!\r\n", n).unwrap();
spi.read_write(&mut read[0..write.len()], write.as_bytes()).await.ok();
info!("read via spi+dma: {}", from_utf8(&read).unwrap());
}
}
struct ZeroClock;
impl Clock for ZeroClock {
fn now(&self) -> u64 {
0
}
}
static EXECUTOR: Forever<Executor> = Forever::new();
#[entry]
fn main() -> ! {
info!("Hello World!");
unsafe {
pac::DBGMCU.cr().modify(|w| {
w.set_dbg_sleep(true);
w.set_dbg_standby(true);
w.set_dbg_stop(true);
});
pac::RCC.ahb1enr().modify(|w| {
w.set_gpioaen(true);
w.set_gpioben(true);
w.set_gpiocen(true);
w.set_gpioden(true);
w.set_gpioeen(true);
w.set_gpiofen(true);
});
}
unsafe { embassy::time::set_clock(&ZeroClock) };
let executor = EXECUTOR.put(Executor::new());
executor.run(|spawner| {
unwrap!(spawner.spawn(main_task()));
})
}

112
examples/stm32h7/src/bin/spi.rs Normal file
View File

@ -0,0 +1,112 @@
#![no_std]
#![no_main]
#![feature(trait_alias)]
#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]
#![feature(type_alias_impl_trait)]
#![allow(incomplete_features)]
#[path = "../example_common.rs"]
mod example_common;
use core::fmt::Write;
use embassy::executor::Executor;
use embassy::time::Clock;
use embassy::util::Forever;
use embassy_stm32::dma::NoDma;
use example_common::*;
use embedded_hal::blocking::spi::Transfer;
use hal::prelude::*;
use stm32h7xx_hal as hal;
use cortex_m_rt::entry;
use stm32h7::stm32h743 as pac;
use heapless::String;
use embassy_stm32::spi::{Spi, Config};
use embassy_stm32::time::Hertz;
#[embassy::task]
async fn main_task() {
let p = embassy_stm32::init(Default::default());
let mut spi = Spi::new(
p.SPI3,
p.PB3,
p.PB5,
p.PB4,
NoDma,
NoDma,
Hertz(1_000_000),
Config::default(),
);
for n in 0u32.. {
let mut write: String<128> = String::new();
core::write!(&mut write, "Hello DMA World {}!\r\n", n).unwrap();
unsafe {
let result = spi.transfer(write.as_bytes_mut());
if let Err(_) = result {
defmt::panic!("crap");
}
}
info!("read via spi: {}", write.as_bytes());
}
}
struct ZeroClock;
impl Clock for ZeroClock {
fn now(&self) -> u64 {
0
}
}
static EXECUTOR: Forever<Executor> = Forever::new();
#[entry]
fn main() -> ! {
info!("Hello World!");
let pp = pac::Peripherals::take().unwrap();
let pwrcfg = pp.PWR.constrain().freeze();
let rcc = pp.RCC.constrain();
rcc.sys_ck(96.mhz())
.pclk1(48.mhz())
.pclk2(48.mhz())
.pclk3(48.mhz())
.pclk4(48.mhz())
.pll1_q_ck(48.mhz())
.freeze(pwrcfg, &pp.SYSCFG);
let pp = unsafe { pac::Peripherals::steal() };
pp.DBGMCU.cr.modify(|_, w| {
w.dbgsleep_d1().set_bit();
w.dbgstby_d1().set_bit();
w.dbgstop_d1().set_bit();
w.d1dbgcken().set_bit();
w
});
pp.RCC.ahb4enr.modify(|_, w| {
w.gpioaen().set_bit();
w.gpioben().set_bit();
w.gpiocen().set_bit();
w.gpioden().set_bit();
w.gpioeen().set_bit();
w.gpiofen().set_bit();
w
});
unsafe { embassy::time::set_clock(&ZeroClock) };
let executor = EXECUTOR.put(Executor::new());
executor.run(|spawner| {
unwrap!(spawner.spawn(main_task()));
})
}

109
examples/stm32h7/src/bin/spi_dma.rs Normal file
View File

@ -0,0 +1,109 @@
#![no_std]
#![no_main]
#![feature(trait_alias)]
#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]
#![feature(type_alias_impl_trait)]
#![allow(incomplete_features)]
#[path = "../example_common.rs"]
mod example_common;
use core::fmt::Write;
use embassy::executor::Executor;
use embassy::time::Clock;
use embassy::util::Forever;
use example_common::*;
use embassy_traits::spi::FullDuplex;
use hal::prelude::*;
use stm32h7xx_hal as hal;
use cortex_m_rt::entry;
use stm32h7::stm32h743 as pac;
use heapless::String;
use embassy_stm32::spi::{Spi, Config};
use embassy_stm32::time::Hertz;
use core::str::from_utf8;
#[embassy::task]
async fn main_task() {
let p = embassy_stm32::init(Default::default());
let mut spi = Spi::new(
p.SPI3,
p.PB3,
p.PB5,
p.PB4,
p.DMA1_CH3,
p.DMA1_CH4,
Hertz(1_000_000),
Config::default(),
);
for n in 0u32.. {
let mut write: String<128> = String::new();
let mut read = [0;128];
core::write!(&mut write, "Hello DMA World {}!\r\n", n).unwrap();
// read_write will slice the &mut read down to &write's actual length.
spi.read_write(&mut read, write.as_bytes()).await.ok();
info!("read via spi+dma: {}", from_utf8(&read).unwrap());
}
}
struct ZeroClock;
impl Clock for ZeroClock {
fn now(&self) -> u64 {
0
}
}
static EXECUTOR: Forever<Executor> = Forever::new();
#[entry]
fn main() -> ! {
info!("Hello World!");
let pp = pac::Peripherals::take().unwrap();
let pwrcfg = pp.PWR.constrain().freeze();
let rcc = pp.RCC.constrain();
rcc.sys_ck(96.mhz())
.pclk1(48.mhz())
.pclk2(48.mhz())
.pclk3(48.mhz())
.pclk4(48.mhz())
.pll1_q_ck(48.mhz())
.freeze(pwrcfg, &pp.SYSCFG);
let pp = unsafe { pac::Peripherals::steal() };
pp.DBGMCU.cr.modify(|_, w| {
w.dbgsleep_d1().set_bit();
w.dbgstby_d1().set_bit();
w.dbgstop_d1().set_bit();
w.d1dbgcken().set_bit();
w
});
pp.RCC.ahb4enr.modify(|_, w| {
w.gpioaen().set_bit();
w.gpioben().set_bit();
w.gpiocen().set_bit();
w.gpioden().set_bit();
w.gpioeen().set_bit();
w.gpiofen().set_bit();
w
});
unsafe { embassy::time::set_clock(&ZeroClock) };
let executor = EXECUTOR.put(Executor::new());
executor.run(|spawner| {
unwrap!(spawner.spawn(main_task()));
})
}

5
examples/stm32l0/src/bin/spi.rs
View File

@ -18,10 +18,11 @@ use embassy_stm32::rcc;
use embassy_stm32::spi::{Config, Spi};
use embassy_stm32::time::Hertz;
use embedded_hal::blocking::spi::Transfer;
use embassy_stm32::dma::NoDma;
#[entry]
fn main() -> ! {
info!("Hello World, dude!");
info!("Hello World, folks!");
let mut p = embassy_stm32::init(Default::default());
let mut rcc = rcc::Rcc::new(p.RCC);
@ -32,6 +33,8 @@ fn main() -> ! {
p.PB3,
p.PA7,
p.PA6,
NoDma,
NoDma,
Hertz(1_000_000),
Config::default(),
);

3
examples/stm32l4/src/bin/spi.rs
View File

@ -17,6 +17,7 @@ use embassy_stm32::time::Hertz;
use embedded_hal::blocking::spi::Transfer;
use embedded_hal::digital::v2::OutputPin;
use example_common::*;
use embassy_stm32::dma::NoDma;
#[entry]
fn main() -> ! {
@ -41,6 +42,8 @@ fn main() -> ! {
p.PC10,
p.PC12,
p.PC11,
NoDma,
NoDma,
Hertz(1_000_000),
Config::default(),
);

116
examples/stm32l4/src/bin/spi_dma.rs Normal file
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@ -0,0 +1,116 @@
#![no_std]
#![no_main]
#![feature(trait_alias)]
#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]
#![feature(type_alias_impl_trait)]
#![allow(incomplete_features)]
#[path = "../example_common.rs"]
mod example_common;
use cortex_m_rt::entry;
use embassy::executor::Executor;
use embassy::time::Clock;
use embassy::util::Forever;
use embassy_stm32::pac;
use example_common::*;
use embassy_stm32::spi::{Spi, Config};
use embassy_traits::spi::FullDuplex;
use embassy_stm32::time::Hertz;
use embassy_stm32::gpio::{Output, Level, Speed, Input, Pull};
use embedded_hal::digital::v2::{OutputPin, InputPin};
#[embassy::task]
async fn main_task() {
let p = embassy_stm32::init(Default::default());
let mut spi = Spi::new(
p.SPI3,
p.PC10,
p.PC12,
p.PC11,
p.DMA1_CH0,
p.DMA1_CH1,
Hertz(1_000_000),
Config::default(),
);
// These are the pins for the Inventek eS-Wifi SPI Wifi Adapter.
let _boot = Output::new(p.PB12, Level::Low, Speed::VeryHigh);
let _wake = Output::new(p.PB13, Level::Low, Speed::VeryHigh);
let mut reset = Output::new(p.PE8, Level::Low, Speed::VeryHigh);
let mut cs = Output::new(p.PE0, Level::High, Speed::VeryHigh);
let ready = Input::new(p.PE1, Pull::Up);
cortex_m::asm::delay(100_000);
reset.set_high().unwrap();
cortex_m::asm::delay(100_000);
while ready.is_low().unwrap() {
info!("waiting for ready");
}
let write = [0x0A; 10];
let mut read = [0; 10];
unwrap!(cs.set_low());
spi.read_write(&mut read, &write).await.ok();
unwrap!(cs.set_high());
info!("xfer {=[u8]:x}", read);
}
struct ZeroClock;
impl Clock for ZeroClock {
fn now(&self) -> u64 {
0
}
}
static EXECUTOR: Forever<Executor> = Forever::new();
#[entry]
fn main() -> ! {
info!("Hello World!");
unsafe {
pac::DBGMCU.cr().modify(|w| {
w.set_dbg_sleep(true);
w.set_dbg_standby(true);
w.set_dbg_stop(true);
});
//pac::RCC.apbenr().modify(|w| {
//w.set_spi3en(true);
// });
pac::RCC.apb2enr().modify(|w| {
w.set_syscfgen(true);
});
pac::RCC.ahb1enr().modify(|w| {
w.set_dmamux1en(true);
w.set_dma1en(true);
w.set_dma2en(true);
});
pac::RCC.ahb2enr().modify(|w| {
w.set_gpioaen(true);
w.set_gpioben(true);
w.set_gpiocen(true);
w.set_gpioden(true);
w.set_gpioeen(true);
w.set_gpiofen(true);
});
}
unsafe { embassy::time::set_clock(&ZeroClock) };
let executor = EXECUTOR.put(Executor::new());
executor.run(|spawner| {
unwrap!(spawner.spawn(main_task()));
})
}