nrf/uart: switch to new interrupt binding.
This commit is contained in:
Dario Nieuwenhuis
@ -10,6 +10,7 @@
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use core::cmp::min;
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::slice;
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use core::sync::atomic::{compiler_fence, AtomicU8, AtomicUsize, Ordering};
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use core::task::Poll;
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@ -23,7 +24,7 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
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use crate::gpio::sealed::Pin;
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use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
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use crate::interrupt::InterruptExt;
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use crate::interrupt::{self, InterruptExt};
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use crate::ppi::{
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self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
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};
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@ -71,211 +72,13 @@ impl State {
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}
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}
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/// Buffered UARTE driver.
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pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
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_peri: PeripheralRef<'d, U>,
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timer: Timer<'d, T>,
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_ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_group: PpiGroup<'d, AnyGroup>,
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/// Interrupt handler.
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pub struct InterruptHandler<U: UarteInstance> {
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_phantom: PhantomData<U>,
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}
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impl<'d, U: UarteInstance, T: TimerInstance> Unpin for BufferedUarte<'d, U, T> {}
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impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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/// Create a new BufferedUarte without hardware flow control.
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_group: impl Peripheral<P = impl Group> + 'd,
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irq: impl Peripheral<P = U::Interrupt> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(rxd, txd, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1.map_into(),
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ppi_ch2.map_into(),
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ppi_group.map_into(),
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irq,
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rxd.map_into(),
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txd.map_into(),
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None,
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None,
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config,
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rx_buffer,
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tx_buffer,
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)
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}
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/// Create a new BufferedUarte with hardware flow control (RTS/CTS)
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new_with_rtscts(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_group: impl Peripheral<P = impl Group> + 'd,
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irq: impl Peripheral<P = U::Interrupt> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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cts: impl Peripheral<P = impl GpioPin> + 'd,
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rts: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(rxd, txd, cts, rts, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1.map_into(),
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ppi_ch2.map_into(),
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ppi_group.map_into(),
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irq,
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rxd.map_into(),
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txd.map_into(),
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Some(cts.map_into()),
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Some(rts.map_into()),
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config,
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rx_buffer,
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tx_buffer,
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)
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}
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fn new_inner(
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peri: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_group: PeripheralRef<'d, AnyGroup>,
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irq: impl Peripheral<P = U::Interrupt> + 'd,
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rxd: PeripheralRef<'d, AnyPin>,
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txd: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(peri, timer, irq);
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assert!(rx_buffer.len() % 2 == 0);
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let r = U::regs();
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = &cts {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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if let Some(pin) = &rts {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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// Initialize state
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let s = U::buffered_state();
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s.tx_count.store(0, Ordering::Relaxed);
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s.rx_bufs.store(0, Ordering::Relaxed);
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let len = tx_buffer.len();
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unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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// Configure
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r.config.write(|w| {
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w.hwfc().bit(false);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// clear errors
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let errors = r.errorsrc.read().bits();
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r.errorsrc.write(|w| unsafe { w.bits(errors) });
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r.events_rxstarted.reset();
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r.events_txstarted.reset();
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r.events_error.reset();
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r.events_endrx.reset();
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r.events_endtx.reset();
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// Enable interrupts
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r.intenclr.write(|w| unsafe { w.bits(!0) });
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r.intenset.write(|w| {
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w.endtx().set();
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w.rxstarted().set();
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w.error().set();
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w
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});
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// Enable UARTE instance
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apply_workaround_for_enable_anomaly(&r);
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r.enable.write(|w| w.enable().enabled());
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// Configure byte counter.
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let mut timer = Timer::new_counter(timer);
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timer.cc(1).write(rx_buffer.len() as u32 * 2);
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timer.cc(1).short_compare_clear();
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timer.clear();
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timer.start();
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let mut ppi_ch1 = Ppi::new_one_to_one(ppi_ch1, Event::from_reg(&r.events_rxdrdy), timer.task_count());
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ppi_ch1.enable();
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s.rx_ppi_ch.store(ppi_ch2.number() as u8, Ordering::Relaxed);
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let mut ppi_group = PpiGroup::new(ppi_group);
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let mut ppi_ch2 = Ppi::new_one_to_two(
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ppi_ch2,
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Event::from_reg(&r.events_endrx),
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Task::from_reg(&r.tasks_startrx),
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ppi_group.task_disable_all(),
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);
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ppi_ch2.disable();
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ppi_group.add_channel(&ppi_ch2);
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irq.disable();
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irq.set_handler(Self::on_interrupt);
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irq.pend();
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irq.enable();
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Self {
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_peri: peri,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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_ppi_group: ppi_group,
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}
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}
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fn pend_irq() {
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unsafe { <U::Interrupt as Interrupt>::steal() }.pend()
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}
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fn on_interrupt(_: *mut ()) {
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impl<U: UarteInstance> interrupt::Handler<U::Interrupt> for InterruptHandler<U> {
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unsafe fn on_interrupt() {
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//trace!("irq: start");
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let r = U::regs();
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let s = U::buffered_state();
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@ -374,6 +177,206 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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//trace!("irq: end");
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}
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}
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/// Buffered UARTE driver.
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pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
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_peri: PeripheralRef<'d, U>,
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timer: Timer<'d, T>,
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_ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_group: PpiGroup<'d, AnyGroup>,
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}
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impl<'d, U: UarteInstance, T: TimerInstance> Unpin for BufferedUarte<'d, U, T> {}
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impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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/// Create a new BufferedUarte without hardware flow control.
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_group: impl Peripheral<P = impl Group> + 'd,
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_irq: impl interrupt::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(rxd, txd, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1.map_into(),
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ppi_ch2.map_into(),
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ppi_group.map_into(),
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rxd.map_into(),
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txd.map_into(),
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None,
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None,
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config,
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rx_buffer,
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tx_buffer,
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)
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}
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/// Create a new BufferedUarte with hardware flow control (RTS/CTS)
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new_with_rtscts(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_group: impl Peripheral<P = impl Group> + 'd,
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_irq: impl interrupt::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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cts: impl Peripheral<P = impl GpioPin> + 'd,
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rts: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(rxd, txd, cts, rts, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1.map_into(),
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ppi_ch2.map_into(),
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ppi_group.map_into(),
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rxd.map_into(),
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txd.map_into(),
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Some(cts.map_into()),
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Some(rts.map_into()),
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config,
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rx_buffer,
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tx_buffer,
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)
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}
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fn new_inner(
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peri: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_group: PeripheralRef<'d, AnyGroup>,
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rxd: PeripheralRef<'d, AnyPin>,
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txd: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(peri, timer);
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assert!(rx_buffer.len() % 2 == 0);
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let r = U::regs();
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = &cts {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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if let Some(pin) = &rts {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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// Initialize state
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let s = U::buffered_state();
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s.tx_count.store(0, Ordering::Relaxed);
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s.rx_bufs.store(0, Ordering::Relaxed);
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let len = tx_buffer.len();
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unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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// Configure
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r.config.write(|w| {
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w.hwfc().bit(false);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// clear errors
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let errors = r.errorsrc.read().bits();
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r.errorsrc.write(|w| unsafe { w.bits(errors) });
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r.events_rxstarted.reset();
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r.events_txstarted.reset();
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r.events_error.reset();
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r.events_endrx.reset();
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r.events_endtx.reset();
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// Enable interrupts
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r.intenclr.write(|w| unsafe { w.bits(!0) });
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r.intenset.write(|w| {
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w.endtx().set();
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w.rxstarted().set();
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w.error().set();
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w
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});
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// Enable UARTE instance
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apply_workaround_for_enable_anomaly(&r);
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r.enable.write(|w| w.enable().enabled());
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// Configure byte counter.
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let mut timer = Timer::new_counter(timer);
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timer.cc(1).write(rx_buffer.len() as u32 * 2);
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timer.cc(1).short_compare_clear();
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timer.clear();
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timer.start();
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let mut ppi_ch1 = Ppi::new_one_to_one(ppi_ch1, Event::from_reg(&r.events_rxdrdy), timer.task_count());
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ppi_ch1.enable();
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s.rx_ppi_ch.store(ppi_ch2.number() as u8, Ordering::Relaxed);
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let mut ppi_group = PpiGroup::new(ppi_group);
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let mut ppi_ch2 = Ppi::new_one_to_two(
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ppi_ch2,
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Event::from_reg(&r.events_endrx),
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Task::from_reg(&r.tasks_startrx),
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ppi_group.task_disable_all(),
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);
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ppi_ch2.disable();
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ppi_group.add_channel(&ppi_ch2);
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unsafe { U::Interrupt::steal() }.pend();
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unsafe { U::Interrupt::steal() }.enable();
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Self {
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_peri: peri,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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_ppi_group: ppi_group,
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}
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}
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fn pend_irq() {
|
||||
unsafe { <U::Interrupt as Interrupt>::steal() }.pend()
|
||||
}
|
||||
|
||||
/// Adjust the baud rate to the provided value.
|
||||
pub fn set_baudrate(&mut self, baudrate: Baudrate) {
|
||||
|
||||
Reference in New Issue
Block a user