Add RTC timer for stm32f4
This commit is contained in:
Thales Fragoso
@ -94,6 +94,66 @@ where
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}
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}
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#[cfg(feature = "stm32f401")]
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mod irqs {
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use super::*;
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declare!(PVD);
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declare!(TAMP_STAMP);
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declare!(RTC_WKUP);
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declare!(FLASH);
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declare!(RCC);
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declare!(EXTI0);
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declare!(EXTI1);
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declare!(EXTI2);
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declare!(EXTI3);
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declare!(EXTI4);
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declare!(DMA1_STREAM0);
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declare!(DMA1_STREAM1);
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declare!(DMA1_STREAM2);
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declare!(DMA1_STREAM3);
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declare!(DMA1_STREAM4);
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declare!(DMA1_STREAM5);
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declare!(DMA1_STREAM6);
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declare!(ADC);
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declare!(EXTI9_5);
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declare!(TIM1_BRK_TIM9);
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declare!(TIM1_UP_TIM10);
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declare!(TIM1_TRG_COM_TIM11);
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declare!(TIM1_CC);
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declare!(TIM2);
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declare!(TIM3);
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declare!(TIM4);
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declare!(I2C1_EV);
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declare!(I2C1_ER);
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declare!(I2C2_EV);
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declare!(I2C2_ER);
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declare!(SPI1);
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declare!(SPI2);
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declare!(USART1);
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declare!(USART2);
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declare!(EXTI15_10);
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declare!(RTC_ALARM);
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declare!(OTG_FS_WKUP);
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declare!(DMA1_STREAM7);
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declare!(SDIO);
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declare!(TIM5);
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declare!(SPI3);
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declare!(DMA2_STREAM0);
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declare!(DMA2_STREAM1);
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declare!(DMA2_STREAM2);
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declare!(DMA2_STREAM3);
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declare!(DMA2_STREAM4);
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declare!(OTG_FS);
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declare!(DMA2_STREAM5);
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declare!(DMA2_STREAM6);
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declare!(DMA2_STREAM7);
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declare!(USART6);
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declare!(I2C3_EV);
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declare!(I2C3_ER);
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declare!(FPU);
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declare!(SPI4);
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}
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#[cfg(feature = "stm32f405")]
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mod irqs {
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use super::*;
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@ -312,6 +312,7 @@ pub(crate) mod fmt;
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pub mod exti;
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pub mod interrupt;
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pub mod rtc;
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pub mod serial;
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pub use cortex_m_rt::interrupt;
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364
embassy-stm32f4/src/rtc.rs
Normal file
364
embassy-stm32f4/src/rtc.rs
Normal file
@ -0,0 +1,364 @@
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use core::cell::Cell;
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use core::convert::TryInto;
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use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
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use embassy::time::{Clock, TICKS_PER_SECOND};
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use stm32f4xx_hal::bb;
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use stm32f4xx_hal::rcc::Clocks;
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use crate::interrupt;
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use crate::interrupt::{CriticalSection, Mutex, OwnedInterrupt};
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// RTC timekeeping works with something we call "periods", which are time intervals
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// of 2^15 ticks. The RTC counter value is 16 bits, so one "overflow cycle" is 2 periods.
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//
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// A `period` count is maintained in parallel to the RTC hardware `counter`, like this:
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// - `period` and `counter` start at 0
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// - `period` is incremented on overflow (at counter value 0)
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// - `period` is incremented "midway" between overflows (at counter value 0x8000)
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//
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// Therefore, when `period` is even, counter is in 0..0x7FFF. When odd, counter is in 0x8000..0xFFFF
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// This allows for now() to return the correct value even if it races an overflow.
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//
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// To get `now()`, `period` is read first, then `counter` is read. If the counter value matches
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// the expected range for the `period` parity, we're done. If it doesn't, this means that
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// a new period start has raced us between reading `period` and `counter`, so we assume the `counter` value
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// corresponds to the next period.
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//
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// `period` is a 32bit integer, so It overflows on 2^32 * 2^15 / 32768 seconds of uptime, which is 136 years.
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fn calc_now(period: u32, counter: u16) -> u64 {
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((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
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}
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struct AlarmState {
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timestamp: Cell<u64>,
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callback: Cell<Option<(fn(*mut ()), *mut ())>>,
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}
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impl AlarmState {
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fn new() -> Self {
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Self {
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timestamp: Cell::new(u64::MAX),
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callback: Cell::new(None),
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}
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}
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}
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// TODO: This is sometimes wasteful, try to find a better way
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const ALARM_COUNT: usize = 3;
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pub struct RTC<T: Instance> {
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rtc: T,
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irq: T::Interrupt,
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/// Number of 2^23 periods elapsed since boot.
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period: AtomicU32,
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/// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
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alarms: Mutex<[AlarmState; ALARM_COUNT]>,
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clocks: Clocks,
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}
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impl<T: Instance> RTC<T> {
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pub fn new(rtc: T, irq: T::Interrupt, clocks: Clocks) -> Self {
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Self {
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rtc,
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irq,
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period: AtomicU32::new(0),
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alarms: Mutex::new([AlarmState::new(), AlarmState::new(), AlarmState::new()]),
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clocks,
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}
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}
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pub fn start(&'static self) {
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self.rtc.enable_clock();
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self.rtc.stop_and_reset();
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let multiplier = if T::ppre(&self.clocks) == 1 { 1 } else { 2 };
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let freq = T::pclk(&self.clocks) * multiplier;
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let psc = freq / TICKS_PER_SECOND as u32 - 1;
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let psc: u16 = psc.try_into().unwrap();
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self.rtc.set_psc_arr(psc, u16::MAX);
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// Mid-way point
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self.rtc.set_compare(0, 0x8000);
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self.rtc.set_compare_interrupt(0, true);
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self.irq.set_handler(
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|ptr| unsafe {
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let this = &*(ptr as *const () as *const Self);
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this.on_interrupt();
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},
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self as *const _ as *mut _,
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);
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self.irq.unpend();
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self.irq.enable();
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self.rtc.start();
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}
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fn on_interrupt(&self) {
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if self.rtc.overflow_interrupt_status() {
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self.rtc.overflow_clear_flag();
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self.next_period();
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}
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// Half overflow
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if self.rtc.compare_interrupt_status(0) {
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self.rtc.compare_clear_flag(0);
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self.next_period();
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}
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for n in 1..=ALARM_COUNT {
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if self.rtc.compare_interrupt_status(n) {
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self.rtc.compare_clear_flag(n);
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interrupt::free(|cs| self.trigger_alarm(n, cs));
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}
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}
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}
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fn next_period(&self) {
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interrupt::free(|cs| {
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let period = self.period.fetch_add(1, Ordering::Relaxed) + 1;
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let t = (period as u64) << 15;
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for n in 1..=ALARM_COUNT {
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let alarm = &self.alarms.borrow(cs)[n - 1];
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let at = alarm.timestamp.get();
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let diff = at - t;
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if diff < 0xc000 {
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self.rtc.set_compare(n, at as u16);
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self.rtc.set_compare_interrupt(n, true);
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}
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}
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})
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}
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fn trigger_alarm(&self, n: usize, cs: &CriticalSection) {
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self.rtc.set_compare_interrupt(n, false);
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let alarm = &self.alarms.borrow(cs)[n - 1];
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alarm.timestamp.set(u64::MAX);
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// Call after clearing alarm, so the callback can set another alarm.
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if let Some((f, ctx)) = alarm.callback.get() {
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f(ctx);
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}
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}
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fn set_alarm_callback(&self, n: usize, callback: fn(*mut ()), ctx: *mut ()) {
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interrupt::free(|cs| {
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let alarm = &self.alarms.borrow(cs)[n - 1];
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alarm.callback.set(Some((callback, ctx)));
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})
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}
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fn set_alarm(&self, n: usize, timestamp: u64) {
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interrupt::free(|cs| {
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let alarm = &self.alarms.borrow(cs)[n - 1];
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alarm.timestamp.set(timestamp);
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let t = self.now();
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if timestamp <= t {
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self.trigger_alarm(n, cs);
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return;
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}
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let diff = timestamp - t;
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if diff < 0xc000 {
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let safe_timestamp = timestamp.max(t + 3);
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self.rtc.set_compare(n, safe_timestamp as u16);
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self.rtc.set_compare_interrupt(n, true);
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} else {
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self.rtc.set_compare_interrupt(n, false);
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}
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})
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}
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pub fn alarm1(&'static self) -> Alarm<T> {
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Alarm { n: 1, rtc: self }
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}
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pub fn alarm2(&'static self) -> Option<Alarm<T>> {
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if T::REAL_ALARM_COUNT >= 2 {
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Some(Alarm { n: 2, rtc: self })
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} else {
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None
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}
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}
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pub fn alarm3(&'static self) -> Option<Alarm<T>> {
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if T::REAL_ALARM_COUNT >= 3 {
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Some(Alarm { n: 3, rtc: self })
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} else {
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None
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}
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}
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}
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impl<T: Instance> embassy::time::Clock for RTC<T> {
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fn now(&self) -> u64 {
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let period = self.period.load(Ordering::Relaxed);
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compiler_fence(Ordering::Acquire);
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let counter = self.rtc.counter();
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calc_now(period, counter)
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}
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}
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pub struct Alarm<T: Instance> {
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n: usize,
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rtc: &'static RTC<T>,
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}
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impl<T: Instance> embassy::time::Alarm for Alarm<T> {
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fn set_callback(&self, callback: fn(*mut ()), ctx: *mut ()) {
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self.rtc.set_alarm_callback(self.n, callback, ctx);
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}
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fn set(&self, timestamp: u64) {
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self.rtc.set_alarm(self.n, timestamp);
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}
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fn clear(&self) {
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self.rtc.set_alarm(self.n, u64::MAX);
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}
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}
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mod sealed {
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pub trait Sealed {}
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}
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pub trait Instance: sealed::Sealed + Sized + 'static {
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type Interrupt: OwnedInterrupt;
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const REAL_ALARM_COUNT: usize;
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fn enable_clock(&self);
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fn set_compare(&self, n: usize, value: u16);
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fn set_compare_interrupt(&self, n: usize, enable: bool);
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fn compare_interrupt_status(&self, n: usize) -> bool;
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fn compare_clear_flag(&self, n: usize);
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fn overflow_interrupt_status(&self) -> bool;
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fn overflow_clear_flag(&self);
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fn set_psc_arr(&self, psc: u16, arr: u16);
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fn stop_and_reset(&self);
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fn start(&self);
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fn counter(&self) -> u16;
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fn ppre(clocks: &Clocks) -> u8;
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fn pclk(clocks: &Clocks) -> u32;
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}
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mod tim2 {
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use super::*;
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use stm32f4xx_hal::pac::{RCC, TIM2};
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impl sealed::Sealed for TIM2 {}
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impl Instance for TIM2 {
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type Interrupt = interrupt::TIM2Interrupt;
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const REAL_ALARM_COUNT: usize = 3;
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fn enable_clock(&self) {
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// NOTE(unsafe) It will only be used for atomic operations
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unsafe {
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let rcc = &*RCC::ptr();
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bb::set(&rcc.apb1enr, 0);
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bb::set(&rcc.apb1rstr, 0);
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bb::clear(&rcc.apb1rstr, 0);
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}
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}
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fn set_compare(&self, n: usize, value: u16) {
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// NOTE(unsafe) these registers accept all the range of u16 values
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match n {
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0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
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1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
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2 => self.ccr3.write(|w| unsafe { w.bits(value.into()) }),
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3 => self.ccr4.write(|w| unsafe { w.bits(value.into()) }),
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_ => {}
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}
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}
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fn set_compare_interrupt(&self, n: usize, enable: bool) {
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if n > 3 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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if enable {
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bb::set(&self.dier, bit);
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} else {
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bb::clear(&self.dier, bit);
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}
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}
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}
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fn compare_interrupt_status(&self, n: usize) -> bool {
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let status = self.sr.read();
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match n {
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0 => status.cc1if().bit_is_set(),
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1 => status.cc2if().bit_is_set(),
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2 => status.cc3if().bit_is_set(),
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3 => status.cc4if().bit_is_set(),
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_ => false,
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}
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}
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fn compare_clear_flag(&self, n: usize) {
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if n > 3 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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bb::clear(&self.sr, bit);
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}
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}
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fn overflow_interrupt_status(&self) -> bool {
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self.sr.read().uif().bit_is_set()
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}
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fn overflow_clear_flag(&self) {
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unsafe {
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bb::clear(&self.sr, 0);
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}
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}
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fn set_psc_arr(&self, psc: u16, arr: u16) {
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// NOTE(unsafe) All u16 values are valid
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self.psc.write(|w| unsafe { w.bits(psc.into()) });
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self.arr.write(|w| unsafe { w.bits(arr.into()) });
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unsafe {
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// Set URS, generate update, clear URS
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bb::set(&self.cr1, 2);
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self.egr.write(|w| w.ug().set_bit());
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bb::clear(&self.cr1, 2);
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}
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}
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fn stop_and_reset(&self) {
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unsafe {
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bb::clear(&self.cr1, 0);
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}
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self.cnt.reset();
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}
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fn start(&self) {
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unsafe { bb::set(&self.cr1, 0) }
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}
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fn counter(&self) -> u16 {
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self.cnt.read().bits() as u16
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}
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fn ppre(clocks: &Clocks) -> u8 {
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clocks.ppre1()
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}
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fn pclk(clocks: &Clocks) -> u32 {
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clocks.pclk1().0
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}
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}
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}
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