Add SPIv1, use cfg_attr to pick correct impl.
Add IRQ to impl_rng!() to accomodate RNG vs HASH_RNG split.
This commit is contained in:
Bob McWhirter
34
embassy-stm32/src/spi/mod.rs
Normal file
34
embassy-stm32/src/spi/mod.rs
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@ -0,0 +1,34 @@
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#![macro_use]
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#[cfg_attr(feature = "_spi_v1", path = "spi_v1.rs")]
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#[cfg_attr(feature = "_spi_v2", path = "spi_v2.rs")]
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mod spi;
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pub use spi::*;
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// TODO move upwards in the tree
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pub enum ByteOrder {
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LsbFirst,
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MsbFirst,
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}
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#[derive(Copy, Clone, PartialOrd, PartialEq)]
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enum WordSize {
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EightBit,
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SixteenBit,
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}
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#[non_exhaustive]
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pub struct Config {
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pub mode: Mode,
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pub byte_order: ByteOrder,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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mode: MODE_0,
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byte_order: ByteOrder::MsbFirst,
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}
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}
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}
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364
embassy-stm32/src/spi/spi_v1.rs
Normal file
364
embassy-stm32/src/spi/spi_v1.rs
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@ -0,0 +1,364 @@
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#![macro_use]
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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use core::marker::PhantomData;
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use embassy::interrupt::Interrupt;
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use embedded_hal::blocking::spi::{Write, Transfer};
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use embassy::util::Unborrow;
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use embassy_extras::{impl_unborrow, unborrow};
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use crate::gpio::{Pin, AnyPin};
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::pac::spi;
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use crate::pac::gpio::Gpio;
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use crate::time::Hertz;
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use crate::spi::{WordSize, Config, ByteOrder};
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impl WordSize {
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fn dff(&self) -> spi::vals::Dff {
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match self {
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WordSize::EightBit => spi::vals::Dff::EIGHTBIT,
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WordSize::SixteenBit => spi::vals::Dff::SIXTEENBIT,
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}
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}
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}
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pub struct Spi<'d, T: Instance> {
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peri: T,
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sck: AnyPin,
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mosi: AnyPin,
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miso: AnyPin,
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current_word_size: WordSize,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Spi<'d, T> {
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pub fn new<F>(pclk: Hertz,
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peri: impl Unborrow<Target=T> + 'd,
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sck: impl Unborrow<Target=impl Sck<T>>,
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mosi: impl Unborrow<Target=impl Mosi<T>>,
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miso: impl Unborrow<Target=impl Miso<T>>,
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>
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{
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unborrow!(peri);
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unborrow!(sck, mosi, miso);
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unsafe {
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Self::configure_pin(sck.block(), sck.pin() as _, sck.af());
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Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af());
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Self::configure_pin(miso.block(), miso.pin() as _, miso.af());
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}
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let sck = sck.degrade();
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let mosi = mosi.degrade();
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let miso = miso.degrade();
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unsafe {
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T::regs().cr2()
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.write(|w| {
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w.set_ssoe(false);
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});
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}
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let br = Self::compute_baud_rate(pclk, freq.into());
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unsafe {
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T::regs().cr1().write(|w| {
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w.set_cpha(
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match config.mode.phase == Phase::CaptureOnSecondTransition {
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true => spi::vals::Cpha::SECONDEDGE,
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false => spi::vals::Cpha::FIRSTEDGE,
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}
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);
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w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
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true => spi::vals::Cpol::IDLEHIGH,
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false => spi::vals::Cpol::IDLELOW,
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});
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w.set_mstr(spi::vals::Mstr::MASTER);
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w.set_br(spi::vals::Br(br));
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w.set_spe(true);
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w.set_lsbfirst(
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match config.byte_order {
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ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST,
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ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST,
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}
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);
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w.set_ssi(true);
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w.set_ssm(true);
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w.set_crcen(false);
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w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL);
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w.set_dff( WordSize::EightBit.dff() )
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});
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}
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Self {
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peri,
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sck,
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mosi,
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miso,
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current_word_size: WordSize::EightBit,
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phantom: PhantomData,
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}
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}
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unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) {
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let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
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block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
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block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num)));
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}
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unsafe fn unconfigure_pin(block: Gpio, pin: usize) {
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let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
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block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG));
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}
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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match clocks.0 / freq.0 {
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0 => unreachable!(),
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1..=2 => 0b000,
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3..=5 => 0b001,
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6..=11 => 0b010,
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12..=23 => 0b011,
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24..=39 => 0b100,
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40..=95 => 0b101,
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96..=191 => 0b110,
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_ => 0b111,
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}
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}
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fn set_word_size(&mut self, word_size: WordSize) {
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if self.current_word_size == word_size {
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return
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}
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unsafe {
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T::regs().cr1().modify( |reg| {
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reg.set_spe(false);
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reg.set_dff( word_size.dff() )
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});
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T::regs().cr1().modify( |reg| {
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reg.set_spe(true);
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});
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self.current_word_size = word_size;
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}
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}
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}
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impl<'d, T: Instance> Drop for Spi<'d, T> {
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fn drop(&mut self) {
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unsafe {
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Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _);
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Self::unconfigure_pin(self.mosi.block(), self.mosi.pin() as _);
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Self::unconfigure_pin(self.miso.block(), self.miso.pin() as _);
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}
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}
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}
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pub enum Error {
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Framing,
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Crc,
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Overrun,
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txe() } {
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// spin
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}
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unsafe {
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regs.dr().write(|reg| reg.0 = *word as u32);
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.fre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crcerr() {
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return Err(Error::Crc);
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}
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if !sr.txe() {
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// loop waiting for TXE
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}
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}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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while unsafe { !regs.sr().read().txe() } {
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// spin
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}
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unsafe {
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regs.dr().write(|reg| reg.0 = *word as u32);
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}
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while unsafe { !regs.sr().read().rxne() } {
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// spin waiting for inbound to shift in.
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}
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*word = unsafe { regs.dr().read().0 as u8 };
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let sr = unsafe { regs.sr().read() };
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if sr.fre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crcerr() {
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return Err(Error::Crc);
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}
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
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type Error = Error;
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fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txe() } {
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// spin
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}
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unsafe {
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regs.dr().write(|reg| reg.0 = *word as u32);
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.fre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crcerr() {
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return Err(Error::Crc);
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}
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if !sr.txe() {
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// loop waiting for TXE
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}
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}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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while unsafe { !regs.sr().read().txe() } {
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// spin
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}
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unsafe {
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regs.dr().write(|reg| reg.0 = *word as u32);
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}
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while unsafe { !regs.sr().read().rxne() } {
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// spin waiting for inbound to shift in.
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}
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*word = unsafe { regs.dr().read().0 as u16 };
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let sr = unsafe { regs.sr().read() };
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if sr.fre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crcerr() {
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return Err(Error::Crc);
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}
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}
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Ok(words)
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}
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}
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pub(crate) mod sealed {
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use super::*;
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use embassy::util::AtomicWaker;
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pub trait Instance {
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fn regs() -> &'static spi::Spi;
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}
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pub trait Sck<T: Instance>: Pin {
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const AF: u8;
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fn af(&self) -> u8 {
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Self::AF
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}
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}
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pub trait Mosi<T: Instance>: Pin {
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const AF: u8;
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fn af(&self) -> u8 {
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Self::AF
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}
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}
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pub trait Miso<T: Instance>: Pin {
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const AF: u8;
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fn af(&self) -> u8 {
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Self::AF
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}
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}
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}
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pub trait Instance: sealed::Instance + 'static {}
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pub trait Sck<T: Instance>: sealed::Sck<T> + 'static {}
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pub trait Mosi<T: Instance>: sealed::Mosi<T> + 'static {}
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pub trait Miso<T: Instance>: sealed::Miso<T> + 'static {}
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macro_rules! impl_spi {
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($inst:ident, $clk:ident) => {
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impl crate::spi::sealed::Instance for peripherals::$inst {
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fn regs() -> &'static crate::pac::spi::Spi {
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&crate::pac::$inst
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}
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}
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impl crate::spi::Instance for peripherals::$inst {}
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};
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}
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macro_rules! impl_spi_pin {
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($inst:ident, $pin_func:ident, $pin:ident, $af:expr) => {
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impl crate::spi::$pin_func<peripherals::$inst> for peripherals::$pin {
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}
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impl crate::spi::sealed::$pin_func<peripherals::$inst> for peripherals::$pin {
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const AF: u8 = $af;
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}
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}
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}
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363
embassy-stm32/src/spi/spi_v2.rs
Normal file
363
embassy-stm32/src/spi/spi_v2.rs
Normal file
@ -0,0 +1,363 @@
|
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#![macro_use]
|
||||
|
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
|
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use core::marker::PhantomData;
|
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use embassy::interrupt::Interrupt;
|
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use embedded_hal::blocking::spi::{Write, Transfer};
|
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use embassy::util::Unborrow;
|
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use embassy_extras::{impl_unborrow, unborrow};
|
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use crate::gpio::{Pin, AnyPin};
|
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use crate::pac::gpio::vals::{Afr, Moder};
|
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use crate::pac::spi;
|
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use crate::pac::gpio::Gpio;
|
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use crate::time::Hertz;
|
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use crate::spi::{WordSize, Config, ByteOrder};
|
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|
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impl WordSize {
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fn ds(&self) -> spi::vals::Ds {
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match self {
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WordSize::EightBit => spi::vals::Ds::EIGHTBIT,
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WordSize::SixteenBit => spi::vals::Ds::SIXTEENBIT,
|
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}
|
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}
|
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|
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fn frxth(&self) -> spi::vals::Frxth {
|
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match self {
|
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WordSize::EightBit => spi::vals::Frxth::QUARTER,
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WordSize::SixteenBit => spi::vals::Frxth::HALF,
|
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}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Spi<'d, T: Instance> {
|
||||
peri: T,
|
||||
sck: AnyPin,
|
||||
mosi: AnyPin,
|
||||
miso: AnyPin,
|
||||
//irq: T::Interrupt,
|
||||
phantom: PhantomData<&'d mut T>,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Spi<'d, T> {
|
||||
pub fn new<F>(pclk: Hertz,
|
||||
peri: impl Unborrow<Target=T> + 'd,
|
||||
sck: impl Unborrow<Target=impl Sck<T>>,
|
||||
mosi: impl Unborrow<Target=impl Mosi<T>>,
|
||||
miso: impl Unborrow<Target=impl Miso<T>>,
|
||||
freq: F,
|
||||
config: Config,
|
||||
) -> Self
|
||||
where
|
||||
F: Into<Hertz>
|
||||
{
|
||||
unborrow!(peri);
|
||||
unborrow!(sck, mosi, miso);
|
||||
|
||||
unsafe {
|
||||
Self::configure_pin(sck.block(), sck.pin() as _, sck.af());
|
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Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af());
|
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Self::configure_pin(miso.block(), miso.pin() as _, miso.af());
|
||||
}
|
||||
|
||||
let sck = sck.degrade();
|
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let mosi = mosi.degrade();
|
||||
let miso = miso.degrade();
|
||||
|
||||
unsafe {
|
||||
T::regs().cr2()
|
||||
.write(|w| {
|
||||
w.set_ssoe(false);
|
||||
});
|
||||
}
|
||||
|
||||
let br = Self::compute_baud_rate(pclk, freq.into());
|
||||
|
||||
unsafe {
|
||||
T::regs().cr1().write(|w| {
|
||||
w.set_cpha(
|
||||
match config.mode.phase == Phase::CaptureOnSecondTransition {
|
||||
true => spi::vals::Cpha::SECONDEDGE,
|
||||
false => spi::vals::Cpha::FIRSTEDGE,
|
||||
}
|
||||
);
|
||||
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
|
||||
true => spi::vals::Cpol::IDLEHIGH,
|
||||
false => spi::vals::Cpol::IDLELOW,
|
||||
});
|
||||
|
||||
w.set_mstr(spi::vals::Mstr::MASTER);
|
||||
w.set_br(spi::vals::Br(br));
|
||||
w.set_spe(true);
|
||||
w.set_lsbfirst(
|
||||
match config.byte_order {
|
||||
ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST,
|
||||
ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST,
|
||||
}
|
||||
);
|
||||
w.set_ssi(true);
|
||||
w.set_ssm(true);
|
||||
w.set_crcen(false);
|
||||
w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL);
|
||||
});
|
||||
}
|
||||
|
||||
Self {
|
||||
peri,
|
||||
sck,
|
||||
mosi,
|
||||
miso,
|
||||
phantom: PhantomData,
|
||||
}
|
||||
}
|
||||
|
||||
unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) {
|
||||
let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
|
||||
block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
|
||||
block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num)));
|
||||
}
|
||||
|
||||
unsafe fn unconfigure_pin(block: Gpio, pin: usize) {
|
||||
let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
|
||||
block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG));
|
||||
}
|
||||
|
||||
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
|
||||
match clocks.0 / freq.0 {
|
||||
0 => unreachable!(),
|
||||
1..=2 => 0b000,
|
||||
3..=5 => 0b001,
|
||||
6..=11 => 0b010,
|
||||
12..=23 => 0b011,
|
||||
24..=39 => 0b100,
|
||||
40..=95 => 0b101,
|
||||
96..=191 => 0b110,
|
||||
_ => 0b111,
|
||||
}
|
||||
}
|
||||
|
||||
fn set_word_size(word_size: WordSize) {
|
||||
unsafe {
|
||||
T::regs().cr2()
|
||||
.write(|w| {
|
||||
w.set_ds(word_size.ds());
|
||||
w.set_frxth(word_size.frxth());
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Drop for Spi<'d, T> {
|
||||
fn drop(&mut self) {
|
||||
unsafe {
|
||||
Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _);
|
||||
Self::unconfigure_pin(self.mosi.block(), self.mosi.pin() as _);
|
||||
Self::unconfigure_pin(self.miso.block(), self.miso.pin() as _);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub enum Error {
|
||||
Framing,
|
||||
Crc,
|
||||
Overrun,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
|
||||
type Error = Error;
|
||||
|
||||
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
|
||||
Self::set_word_size(WordSize::EightBit);
|
||||
let regs = T::regs();
|
||||
|
||||
for word in words.iter() {
|
||||
while unsafe { !regs.sr().read().txe() } {
|
||||
// spin
|
||||
}
|
||||
unsafe {
|
||||
regs.dr().write(|reg| reg.0 = *word as u32);
|
||||
}
|
||||
loop {
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
if sr.fre() {
|
||||
return Err(Error::Framing);
|
||||
}
|
||||
if sr.ovr() {
|
||||
return Err(Error::Overrun);
|
||||
}
|
||||
if sr.crcerr() {
|
||||
return Err(Error::Crc);
|
||||
}
|
||||
if !sr.txe() {
|
||||
// loop waiting for TXE
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
|
||||
type Error = Error;
|
||||
|
||||
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
|
||||
Self::set_word_size(WordSize::EightBit);
|
||||
let regs = T::regs();
|
||||
|
||||
for word in words.iter_mut() {
|
||||
while unsafe { !regs.sr().read().txe() } {
|
||||
// spin
|
||||
}
|
||||
unsafe {
|
||||
regs.dr().write(|reg| reg.0 = *word as u32);
|
||||
}
|
||||
while unsafe { !regs.sr().read().rxne() } {
|
||||
// spin waiting for inbound to shift in.
|
||||
}
|
||||
*word = unsafe { regs.dr().read().0 as u8 };
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
if sr.fre() {
|
||||
return Err(Error::Framing);
|
||||
}
|
||||
if sr.ovr() {
|
||||
return Err(Error::Overrun);
|
||||
}
|
||||
if sr.crcerr() {
|
||||
return Err(Error::Crc);
|
||||
}
|
||||
}
|
||||
|
||||
Ok(words)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
|
||||
type Error = Error;
|
||||
|
||||
fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
|
||||
Self::set_word_size(WordSize::SixteenBit);
|
||||
let regs = T::regs();
|
||||
|
||||
for word in words.iter() {
|
||||
while unsafe { !regs.sr().read().txe() } {
|
||||
// spin
|
||||
}
|
||||
unsafe {
|
||||
regs.dr().write(|reg| reg.0 = *word as u32);
|
||||
}
|
||||
loop {
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
if sr.fre() {
|
||||
return Err(Error::Framing);
|
||||
}
|
||||
if sr.ovr() {
|
||||
return Err(Error::Overrun);
|
||||
}
|
||||
if sr.crcerr() {
|
||||
return Err(Error::Crc);
|
||||
}
|
||||
if !sr.txe() {
|
||||
// loop waiting for TXE
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> {
|
||||
type Error = Error;
|
||||
|
||||
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
|
||||
Self::set_word_size(WordSize::SixteenBit);
|
||||
let regs = T::regs();
|
||||
|
||||
for word in words.iter_mut() {
|
||||
while unsafe { !regs.sr().read().txe() } {
|
||||
// spin
|
||||
}
|
||||
unsafe {
|
||||
regs.dr().write(|reg| reg.0 = *word as u32);
|
||||
}
|
||||
while unsafe { !regs.sr().read().rxne() } {
|
||||
// spin waiting for inbound to shift in.
|
||||
}
|
||||
*word = unsafe { regs.dr().read().0 as u16 };
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
if sr.fre() {
|
||||
return Err(Error::Framing);
|
||||
}
|
||||
if sr.ovr() {
|
||||
return Err(Error::Overrun);
|
||||
}
|
||||
if sr.crcerr() {
|
||||
return Err(Error::Crc);
|
||||
}
|
||||
}
|
||||
|
||||
Ok(words)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use super::*;
|
||||
use embassy::util::AtomicWaker;
|
||||
|
||||
pub trait Instance {
|
||||
fn regs() -> &'static spi::Spi;
|
||||
}
|
||||
|
||||
pub trait Sck<T: Instance>: Pin {
|
||||
const AF: u8;
|
||||
fn af(&self) -> u8 {
|
||||
Self::AF
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Mosi<T: Instance>: Pin {
|
||||
const AF: u8;
|
||||
fn af(&self) -> u8 {
|
||||
Self::AF
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Miso<T: Instance>: Pin {
|
||||
const AF: u8;
|
||||
fn af(&self) -> u8 {
|
||||
Self::AF
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Instance: sealed::Instance + 'static {}
|
||||
|
||||
pub trait Sck<T: Instance>: sealed::Sck<T> + 'static {}
|
||||
|
||||
pub trait Mosi<T: Instance>: sealed::Mosi<T> + 'static {}
|
||||
|
||||
pub trait Miso<T: Instance>: sealed::Miso<T> + 'static {}
|
||||
|
||||
macro_rules! impl_spi {
|
||||
($inst:ident, $clk:ident) => {
|
||||
impl crate::spi::sealed::Instance for peripherals::$inst {
|
||||
fn regs() -> &'static crate::pac::spi::Spi {
|
||||
&crate::pac::$inst
|
||||
}
|
||||
}
|
||||
|
||||
impl crate::spi::Instance for peripherals::$inst {}
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! impl_spi_pin {
|
||||
($inst:ident, $pin_func:ident, $pin:ident, $af:expr) => {
|
||||
impl crate::spi::$pin_func<peripherals::$inst> for peripherals::$pin {
|
||||
}
|
||||
|
||||
impl crate::spi::sealed::$pin_func<peripherals::$inst> for peripherals::$pin {
|
||||
const AF: u8 = $af;
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user