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Merge #652 #653

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652: Use new stm32-data registers and fix AHB clock calculation r=Dirbaio a=msamsonoff

This is the follow-on to my PR against stm32-data that added new register enums for the G0. I have updated the G0 RCC module to use those new enums.

I have also fixed an issue with the calculation of the AHB clock rate. 32 is not available as an AHB prescaler. The sequence jumps from 16 to 64. The original bit shifting math did not account for this gap. I have replaced it with a `match` instead.

653: Fixes for rustdoc building. r=Dirbaio a=Dirbaio



Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
This commit is contained in:
bors[bot]
2022-03-04 17:07:04 +00:00
committed by GitHub
parent 35636953b2 609975f821 265cd1115b
commit 9ebf7eee6d
18 changed files with 136 additions and 57 deletions
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1
embassy-stm32/src/can/bxcan.rs
View File

@ -7,6 +7,7 @@ use embassy_hal_common::unborrow;
use crate::gpio::sealed::AFType;
use crate::{peripherals, rcc::RccPeripheral};
#[doc(no_inline)]
pub use bxcan::*;
pub struct Can<'d, T: Instance + bxcan::Instance> {

4
embassy-stm32/src/dma/bdma.rs
View File

@ -6,8 +6,8 @@ use core::task::Waker;
use embassy::interrupt::{Interrupt, InterruptExt};
use embassy::waitqueue::AtomicWaker;
use crate::_generated::BDMA_CHANNEL_COUNT;
use crate::dma::Request;
use crate::generated::BDMA_CHANNEL_COUNT;
use crate::pac;
use crate::pac::bdma::vals;
@ -65,7 +65,7 @@ pub(crate) unsafe fn init() {
crate::interrupt::$irq::steal().enable();
};
}
crate::generated::init_bdma();
crate::_generated::init_bdma();
}
foreach_dma_channel! {

4
embassy-stm32/src/dma/dma.rs
View File

@ -4,7 +4,7 @@ use core::task::Waker;
use embassy::interrupt::{Interrupt, InterruptExt};
use embassy::waitqueue::AtomicWaker;
use crate::generated::DMA_CHANNEL_COUNT;
use crate::_generated::DMA_CHANNEL_COUNT;
use crate::interrupt;
use crate::pac;
use crate::pac::dma::{regs, vals};
@ -59,7 +59,7 @@ pub(crate) unsafe fn init() {
interrupt::$irq::steal().enable();
};
}
crate::generated::init_dma();
crate::_generated::init_dma();
}
foreach_dma_channel! {

2
embassy-stm32/src/dma/dmamux.rs
View File

@ -49,5 +49,5 @@ foreach_dma_channel! {
/// safety: must be called only once
pub(crate) unsafe fn init() {
crate::generated::init_dmamux();
crate::_generated::init_dmamux();
}

2
embassy-stm32/src/gpio.rs
View File

@ -574,7 +574,7 @@ foreach_pin!(
);
pub(crate) unsafe fn init() {
crate::generated::init_gpio();
crate::_generated::init_gpio();
}
mod eh02 {

2
embassy-stm32/src/interrupt.rs
View File

@ -3,4 +3,4 @@ pub use critical_section::CriticalSection;
pub use embassy::interrupt::{take, Interrupt};
pub use embassy_hal_common::interrupt::Priority4 as Priority;
pub use crate::generated::interrupt::*;
pub use crate::_generated::interrupt::*;

9
embassy-stm32/src/lib.rs
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@ -11,7 +11,7 @@ pub(crate) use stm32_metapac as pac;
// This must go FIRST so that all the other modules see its macros.
pub mod fmt;
include!(concat!(env!("OUT_DIR"), "/macros.rs"));
include!(concat!(env!("OUT_DIR"), "/_macros.rs"));
// Utilities
pub mod interrupt;
@ -63,16 +63,15 @@ pub mod usb_otg;
pub mod subghz;
// This must go last, so that it sees all the impl_foo! macros defined earlier.
pub(crate) mod generated {
pub(crate) mod _generated {
#![allow(dead_code)]
#![allow(unused_imports)]
#![allow(non_snake_case)]
include!(concat!(env!("OUT_DIR"), "/generated.rs"));
include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
}
pub use _generated::{peripherals, Peripherals};
pub use embassy_macros::interrupt;
pub use generated::{peripherals, Peripherals};
#[non_exhaustive]
pub struct Config {

87
embassy-stm32/src/rcc/g0.rs
View File

@ -1,3 +1,4 @@
use crate::pac::rcc::vals::{Hpre, Hsidiv, Ppre, Sw};
use crate::pac::{PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@ -29,17 +30,17 @@ pub enum HSI16Prescaler {
Div128,
}
impl Into<u8> for HSI16Prescaler {
fn into(self) -> u8 {
impl Into<Hsidiv> for HSI16Prescaler {
fn into(self) -> Hsidiv {
match self {
HSI16Prescaler::NotDivided => 0x00,
HSI16Prescaler::Div2 => 0x01,
HSI16Prescaler::Div4 => 0x02,
HSI16Prescaler::Div8 => 0x03,
HSI16Prescaler::Div16 => 0x04,
HSI16Prescaler::Div32 => 0x05,
HSI16Prescaler::Div64 => 0x06,
HSI16Prescaler::Div128 => 0x07,
HSI16Prescaler::NotDivided => Hsidiv::DIV1,
HSI16Prescaler::Div2 => Hsidiv::DIV2,
HSI16Prescaler::Div4 => Hsidiv::DIV4,
HSI16Prescaler::Div8 => Hsidiv::DIV8,
HSI16Prescaler::Div16 => Hsidiv::DIV16,
HSI16Prescaler::Div32 => Hsidiv::DIV32,
HSI16Prescaler::Div64 => Hsidiv::DIV64,
HSI16Prescaler::Div128 => Hsidiv::DIV128,
}
}
}
@ -68,30 +69,30 @@ pub enum APBPrescaler {
Div16,
}
impl Into<u8> for APBPrescaler {
fn into(self) -> u8 {
impl Into<Ppre> for APBPrescaler {
fn into(self) -> Ppre {
match self {
APBPrescaler::NotDivided => 1,
APBPrescaler::Div2 => 0x04,
APBPrescaler::Div4 => 0x05,
APBPrescaler::Div8 => 0x06,
APBPrescaler::Div16 => 0x07,
APBPrescaler::NotDivided => Ppre::DIV1,
APBPrescaler::Div2 => Ppre::DIV2,
APBPrescaler::Div4 => Ppre::DIV4,
APBPrescaler::Div8 => Ppre::DIV8,
APBPrescaler::Div16 => Ppre::DIV16,
}
}
}
impl Into<u8> for AHBPrescaler {
fn into(self) -> u8 {
impl Into<Hpre> for AHBPrescaler {
fn into(self) -> Hpre {
match self {
AHBPrescaler::NotDivided => 1,
AHBPrescaler::Div2 => 0x08,
AHBPrescaler::Div4 => 0x09,
AHBPrescaler::Div8 => 0x0a,
AHBPrescaler::Div16 => 0x0b,
AHBPrescaler::Div64 => 0x0c,
AHBPrescaler::Div128 => 0x0d,
AHBPrescaler::Div256 => 0x0e,
AHBPrescaler::Div512 => 0x0f,
AHBPrescaler::NotDivided => Hpre::DIV1,
AHBPrescaler::Div2 => Hpre::DIV2,
AHBPrescaler::Div4 => Hpre::DIV4,
AHBPrescaler::Div8 => Hpre::DIV8,
AHBPrescaler::Div16 => Hpre::DIV16,
AHBPrescaler::Div64 => Hpre::DIV64,
AHBPrescaler::Div128 => Hpre::DIV128,
AHBPrescaler::Div256 => Hpre::DIV256,
AHBPrescaler::Div512 => Hpre::DIV512,
}
}
}
@ -120,27 +121,27 @@ pub(crate) unsafe fn init(config: Config) {
let (sys_clk, sw) = match config.mux {
ClockSrc::HSI16(div) => {
// Enable HSI16
let div: u8 = div.into();
let div: Hsidiv = div.into();
RCC.cr().write(|w| {
w.set_hsidiv(div);
w.set_hsion(true)
});
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ >> div, 0x00)
(HSI_FREQ >> div.0, Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq.0, 0x01)
(freq.0, Sw::HSE)
}
ClockSrc::LSI => {
// Enable LSI
RCC.csr().write(|w| w.set_lsion(true));
while !RCC.csr().read().lsirdy() {}
(LSI_FREQ, 0x03)
(LSI_FREQ, Sw::LSI)
}
};
@ -150,20 +151,24 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre(config.apb_pre.into());
});
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::NotDivided => sys_clk,
pre => {
let pre: u8 = pre.into();
let pre = 1 << (pre as u32 - 7);
sys_clk / pre
}
let ahb_div = match config.ahb_pre {
AHBPrescaler::NotDivided => 1,
AHBPrescaler::Div2 => 2,
AHBPrescaler::Div4 => 4,
AHBPrescaler::Div8 => 8,
AHBPrescaler::Div16 => 16,
AHBPrescaler::Div64 => 64,
AHBPrescaler::Div128 => 128,
AHBPrescaler::Div256 => 256,
AHBPrescaler::Div512 => 512,
};
let ahb_freq = sys_clk / ahb_div;
let (apb_freq, apb_tim_freq) = match config.apb_pre {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => {
let pre: u8 = pre.into();
let pre: u8 = 1 << (pre - 3);
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.0 - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}