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stm32: add lp to l0

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This commit is contained in:
xoviat
2023-09-14 18:53:27 -05:00
parent 309c3d6b47
commit 9fb14379c3
5 changed files with 48 additions and 6 deletions
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4
embassy-stm32/src/rcc/bd.rs
View File

@ -58,13 +58,13 @@ impl BackupDomain {
))]
#[allow(dead_code, unused_variables)]
fn modify<R>(f: impl FnOnce(&mut Bdcr) -> R) -> R {
#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1, rtc_v2l0))]
let cr = crate::pac::PWR.cr();
#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
let cr = crate::pac::PWR.cr1();
// TODO: Missing from PAC for l0 and f0?
#[cfg(not(any(rtc_v2f0, rtc_v2l0, rtc_v3u5)))]
#[cfg(not(any(rtc_v2f0, rtc_v3u5)))]
{
cr.modify(|w| w.set_dbp(true));
while !cr.read().dbp() {}

8
embassy-stm32/src/rcc/l0.rs
View File

@ -1,4 +1,6 @@
use super::bd::BackupDomain;
pub use super::bus::{AHBPrescaler, APBPrescaler};
use super::RtcClockSource;
use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
use crate::pac::RCC;
#[cfg(crs)]
@ -135,6 +137,7 @@ pub struct Config {
pub apb2_pre: APBPrescaler,
#[cfg(crs)]
pub enable_hsi48: bool,
pub rtc: Option<RtcClockSource>,
}
impl Default for Config {
@ -147,6 +150,7 @@ impl Default for Config {
apb2_pre: APBPrescaler::NotDivided,
#[cfg(crs)]
enable_hsi48: false,
rtc: None,
}
}
}
@ -231,6 +235,10 @@ pub(crate) unsafe fn init(config: Config) {
}
};
config.rtc.map(|rtc| {
BackupDomain::configure_ls(rtc, None);
});
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(config.ahb_pre.into());