max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

restrict unsafe block

Browse Source
This commit is contained in:
xoviat 2021-01-06 21:02:02 -06:00
parent 31ba052f14
commit a168b9ef51
2 changed files with 53 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
embassy-stm32f4-examples/src/serial.rs
View File

@ -28,8 +28,8 @@ async fn run(dp: stm32::Peripherals, cp: cortex_m::Peripherals) {
.pclk1(24.mhz())
.freeze();
unsafe {
let mut serial = serial::Serial::new(
let mut serial = unsafe {
serial::Serial::new(
gpioa.pa9.into_alternate_af7(),
gpioa.pa10.into_alternate_af7(),
interrupt::take!(DMA2_STREAM7),
@ -40,13 +40,13 @@ async fn run(dp: stm32::Peripherals, cp: cortex_m::Peripherals) {
config::Parity::ParityNone,
9600.bps(),
clocks,
);
)
};
let buf = singleton!(: [u8; 30] = [0; 30]).unwrap();
buf[5] = 0x01;
serial.send(buf).await;
}
}
static EXECUTOR: Forever<Executor> = Forever::new();

10
embassy-stm32f4/src/serial.rs
View File

@ -152,8 +152,7 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
fn send<'a>(&'a mut self, buf: &'a [u8]) -> Self::SendFuture<'a> {
unsafe { INSTANCE = self };
unsafe {
let static_buf = core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf);
let static_buf = unsafe { core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf) };
let tx_stream = self.tx_stream.take().unwrap();
let usart = self.usart.take().unwrap();
@ -184,7 +183,6 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
Ok(())
}
}
}
/// Receives serial data.
///
@ -199,8 +197,7 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
fn receive<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReceiveFuture<'a> {
unsafe { INSTANCE = self };
unsafe {
let static_buf = core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf);
let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
let rx_stream = self.rx_stream.take().unwrap();
let usart = self.usart.take().unwrap();
STATE.rx_int.reset();
@ -219,11 +216,10 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
self.rx_int.enable();
rx_transfer.start(|_usart| {});
STATE.rx_int.wait().await;
let (rx_stream, usart, buf, _) = rx_transfer.free();
let (rx_stream, usart, _, _) = rx_transfer.free();
self.rx_stream.replace(rx_stream);
self.usart.replace(usart);
Ok(())
}
}
}
}