stm32/test: fix race condition in uart_dma.
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@ -6,6 +6,7 @@
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mod example_common;
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mod example_common;
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use defmt::assert_eq;
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use defmt::assert_eq;
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use embassy_executor::Spawner;
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use embassy_executor::Spawner;
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use embassy_futures::join::join;
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use embassy_stm32::interrupt;
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use embassy_stm32::interrupt;
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use embassy_stm32::usart::{Config, Uart};
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use embassy_stm32::usart::{Config, Uart};
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use example_common::*;
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use example_common::*;
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@ -76,18 +77,26 @@ async fn main(_spawner: Spawner) {
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(p.PB6, p.PB7, p.USART1, interrupt::take!(USART1), p.DMA1_CH1, p.DMA1_CH2);
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(p.PB6, p.PB7, p.USART1, interrupt::take!(USART1), p.DMA1_CH1, p.DMA1_CH2);
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let config = Config::default();
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let config = Config::default();
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let mut usart = Uart::new(usart, rx, tx, irq, tx_dma, rx_dma, config);
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let usart = Uart::new(usart, rx, tx, irq, tx_dma, rx_dma, config);
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// We can't send too many bytes, they have to fit in the FIFO.
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const LEN: usize = 128;
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// This is because we aren't sending+receiving at the same time.
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let mut tx_buf = [0; LEN];
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// For whatever reason, blocking works with 2 bytes but DMA only with 1??
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let mut rx_buf = [0; LEN];
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for i in 0..LEN {
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tx_buf[i] = i as u8;
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}
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let data = [0x42];
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let (mut tx, mut rx) = usart.split();
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usart.write(&data).await.unwrap();
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let mut buf = [0; 1];
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let tx_fut = async {
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usart.read(&mut buf).await.unwrap();
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tx.write(&tx_buf).await.unwrap();
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assert_eq!(buf, data);
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};
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let rx_fut = async {
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rx.read(&mut rx_buf).await.unwrap();
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};
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join(rx_fut, tx_fut).await;
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assert_eq!(tx_buf, rx_buf);
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info!("Test OK");
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info!("Test OK");
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cortex_m::asm::bkpt();
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cortex_m::asm::bkpt();
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