Add half duplex support
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4695e46a59
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@ -161,6 +161,10 @@ pub struct Config {
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/// Set this to true to invert RX pin signal values (V<sub>DD</sub> =0/mark, Gnd = 1/idle).
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/// Set this to true to invert RX pin signal values (V<sub>DD</sub> =0/mark, Gnd = 1/idle).
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#[cfg(any(usart_v3, usart_v4))]
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#[cfg(any(usart_v3, usart_v4))]
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pub invert_rx: bool,
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pub invert_rx: bool,
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/// enable single wire half duplex communication. Only the tx pin is used. Needs an external
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/// pull up
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pub half_duplex: bool,
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}
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}
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impl Default for Config {
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impl Default for Config {
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@ -180,6 +184,7 @@ impl Default for Config {
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invert_tx: false,
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invert_tx: false,
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#[cfg(any(usart_v3, usart_v4))]
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#[cfg(any(usart_v3, usart_v4))]
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invert_rx: false,
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invert_rx: false,
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half_duplex: false,
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}
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}
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}
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}
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}
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}
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@ -811,19 +816,27 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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let r = T::regs();
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let r = T::regs();
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// Some chips do not have swap_rx_tx bit
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// Some chips do not have swap_rx_tx bit
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cfg_if::cfg_if! {
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if config.half_duplex {
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if #[cfg(any(usart_v3, usart_v4))] {
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if config.swap_rx_tx {
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if config.swap_rx_tx {
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rx.set_as_af(rx.af_num(), AFType::OutputOpenDrain);
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let (rx, tx) = (tx, rx);
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} else {
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputOpenDrain);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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} else {
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cfg_if::cfg_if! {
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if #[cfg(any(usart_v3, usart_v4))] {
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if config.swap_rx_tx {
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let (rx, tx) = (tx, rx);
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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} else {
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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} else {
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} else {
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rx.set_as_af(rx.af_num(), AFType::Input);
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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}
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} else {
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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}
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}
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}
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@ -1039,6 +1052,7 @@ fn configure(
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#[cfg(not(usart_v1))]
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#[cfg(not(usart_v1))]
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r.cr3().modify(|w| {
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r.cr3().modify(|w| {
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w.set_onebit(config.assume_noise_free);
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w.set_onebit(config.assume_noise_free);
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w.set_hdsel(config.half_duplex);
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});
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});
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r.cr1().write(|w| {
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r.cr1().write(|w| {
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