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stm32: update metapac

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This commit is contained in:
xoviat
2023-10-16 20:04:10 -05:00
parent f7980885a5
commit a3574e519a
11 changed files with 54 additions and 25 deletions
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2
embassy-stm32/src/rcc/c0.rs
View File

@ -134,6 +134,8 @@ pub(crate) unsafe fn init(config: Config) {
};
set_freqs(Clocks {
hsi: None,
lse: None,
sys: sys_clk,
hclk1: ahb_freq,
pclk1: apb_freq,

4
embassy-stm32/src/rcc/l0l1.rs
View File

@ -31,7 +31,7 @@ pub enum PLLSource {
impl From<PLLSource> for Pllsrc {
fn from(val: PLLSource) -> Pllsrc {
match val {
PLLSource::HSI16 => Pllsrc::HSI16,
PLLSource::HSI16 => Pllsrc::HSI,
PLLSource::HSE(_) => Pllsrc::HSE,
}
}
@ -88,7 +88,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().write(|w| w.set_hsi16on(true));
while !RCC.cr().read().hsi16rdy() {}
(HSI_FREQ, Sw::HSI16)
(HSI_FREQ, Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE

25
embassy-stm32/src/rcc/l4l5.rs
View File

@ -187,7 +187,10 @@ pub(crate) unsafe fn init(config: Config) {
let sys_clk = match config.mux {
ClockSrc::HSE => hse.unwrap(),
#[cfg(rcc_l5)]
ClockSrc::HSI16 => hsi16.unwrap(),
#[cfg(not(rcc_l5))]
ClockSrc::HSI => hsi16.unwrap(),
ClockSrc::MSI => msi.unwrap(),
ClockSrc::PLL => pll._r.unwrap(),
};
@ -200,7 +203,10 @@ pub(crate) unsafe fn init(config: Config) {
Clk48Src::HSI48 => hsi48,
Clk48Src::MSI => msi,
Clk48Src::PLLSAI1_Q => pllsai1._q,
#[cfg(rcc_l5)]
Clk48Src::PLL_Q => pll._q,
#[cfg(not(rcc_l5))]
Clk48Src::PLL1_Q => pll._q,
};
#[cfg(rcc_l4plus)]
@ -266,6 +272,22 @@ pub(crate) unsafe fn init(config: Config) {
pclk2: apb2_freq,
pclk1_tim: apb1_tim_freq,
pclk2_tim: apb2_tim_freq,
#[cfg(rcc_l4)]
hsi: None,
#[cfg(rcc_l4)]
lse: None,
#[cfg(rcc_l4)]
pllsai1_p: None,
#[cfg(rcc_l4)]
pllsai2_p: None,
#[cfg(rcc_l4)]
pll1_p: None,
#[cfg(rcc_l4)]
pll1_q: None,
#[cfg(rcc_l4)]
sai1_extclk: None,
#[cfg(rcc_l4)]
sai2_extclk: None,
rtc,
});
}
@ -341,7 +363,10 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
let pll_src = match pll.source {
PLLSource::NONE => panic!("must not select PLL source as NONE"),
PLLSource::HSE => input.hse,
#[cfg(rcc_l5)]
PLLSource::HSI16 => input.hsi16,
#[cfg(not(rcc_l5))]
PLLSource::HSI => input.hsi16,
PLLSource::MSI => input.msi,
};

16
embassy-stm32/src/rcc/mod.rs
View File

@ -110,14 +110,18 @@ pub struct Clocks {
#[cfg(all(rcc_f4, not(stm32f410)))]
pub plli2s1_r: Option<Hertz>,
#[cfg(rcc_l4)]
pub pllsai1_p: Option<Hertz>,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai1_q: Option<Hertz>,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai1_r: Option<Hertz>,
#[cfg(rcc_l4)]
pub pllsai2_p: Option<Hertz>,
#[cfg(stm32g4)]
#[cfg(any(stm32g4, rcc_l4))]
pub pll1_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
#[cfg(any(stm32h5, stm32h7, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_l4))]
pub pll1_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_p: Option<Hertz>,
@ -154,7 +158,7 @@ pub struct Clocks {
pub rtc: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
pub hsi: Option<Hertz>,
#[cfg(stm32h5)]
pub hsi48: Option<Hertz>,
@ -163,7 +167,7 @@ pub struct Clocks {
#[cfg(any(stm32h5, stm32h7))]
pub csi: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
pub lse: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub hse: Option<Hertz>,
@ -175,6 +179,10 @@ pub struct Clocks {
#[cfg(stm32h7)]
pub rcc_pclk_d3: Option<Hertz>,
#[cfg(rcc_l4)]
pub sai1_extclk: Option<Hertz>,
#[cfg(rcc_l4)]
pub sai2_extclk: Option<Hertz>,
}
#[cfg(feature = "low-power")]