uarte: Only stop TX forcefully when a transmissions is running
This comes with insignificant power consumption improvements but makes the code of the RX and TX case symmetric.
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a7c03e4cb6
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@ -156,6 +156,13 @@ where
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uarte.events_endtx.reset();
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trace!("endtx");
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compiler_fence(Ordering::SeqCst);
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if uarte.events_txstarted.read().bits() != 0 {
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// The ENDTX was signal triggered because DMA has finished.
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uarte.events_txstarted.reset();
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try_disable = true;
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}
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T::state().tx_done.signal(());
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}
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@ -211,6 +218,7 @@ impl<T: Instance> embassy::uart::Uart for Uarte<T> {
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// `mem::forget()` on a previous future after polling it once.
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assert!(!self.tx_started());
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T::state().tx_done.reset();
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self.enable();
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SendFuture {
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@ -281,11 +289,9 @@ where
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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let Self { uarte, buf } = unsafe { self.get_unchecked_mut() };
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if !uarte.tx_started() {
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match T::state().tx_done.poll_wait(cx) {
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Poll::Pending if !uarte.tx_started() => {
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let uarte = &uarte.instance;
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T::state().tx_done.reset();
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let ptr = buf.as_ptr();
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let len = buf.len();
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assert!(len <= EASY_DMA_SIZE);
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@ -300,9 +306,11 @@ where
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trace!("starttx");
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uarte.tasks_starttx.write(|w| unsafe { w.bits(1) });
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Poll::Pending
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}
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Poll::Pending => Poll::Pending,
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Poll::Ready(_) => Poll::Ready(Ok(())),
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}
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T::state().tx_done.poll_wait(cx).map(|()| Ok(()))
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}
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}
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