stm32: update configure_ls as agreed
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@ -1,5 +1,5 @@
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#[allow(dead_code)]
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#[derive(Default)]
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#[derive(Default, Clone, Copy)]
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pub enum LseDrive {
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#[cfg(any(rtc_v2f7, rtc_v2l4))]
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Low = 0,
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@ -87,40 +87,42 @@ impl BackupDomain {
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rtc_v3u5
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))]
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#[allow(dead_code, unused_variables)]
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pub fn configure_ls(clock_source: RtcClockSource, lse_drive: Option<LseDrive>) {
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match clock_source {
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RtcClockSource::LSI => {
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#[cfg(rtc_v3u5)]
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let csr = crate::pac::RCC.bdcr();
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pub fn configure_ls(clock_source: RtcClockSource, lsi: bool, lse: Option<LseDrive>) {
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if lsi {
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#[cfg(rtc_v3u5)]
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let csr = crate::pac::RCC.bdcr();
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#[cfg(not(rtc_v3u5))]
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let csr = crate::pac::RCC.csr();
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Self::modify(|_| {
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#[cfg(not(any(rcc_wb, rcc_wba)))]
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csr.modify(|w| w.set_lsion(true));
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#[cfg(any(rcc_wb, rcc_wba))]
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csr.modify(|w| w.set_lsi1on(true));
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});
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#[cfg(not(rtc_v3u5))]
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let csr = crate::pac::RCC.csr();
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Self::modify(|_| {
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#[cfg(not(any(rcc_wb, rcc_wba)))]
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while !csr.read().lsirdy() {}
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csr.modify(|w| w.set_lsion(true));
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#[cfg(any(rcc_wb, rcc_wba))]
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while !csr.read().lsi1rdy() {}
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}
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RtcClockSource::LSE => {
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let lse_drive = lse_drive.unwrap_or_default();
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csr.modify(|w| w.set_lsi1on(true));
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});
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Self::modify(|w| {
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#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
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w.set_lsedrv(lse_drive.into());
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w.set_lseon(true);
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});
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#[cfg(not(any(rcc_wb, rcc_wba)))]
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while !csr.read().lsirdy() {}
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while !Self::read().lserdy() {}
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}
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#[cfg(any(rcc_wb, rcc_wba))]
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while !csr.read().lsi1rdy() {}
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}
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if let Some(lse_drive) = lse {
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Self::modify(|w| {
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#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
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w.set_lsedrv(lse_drive.into());
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w.set_lseon(true);
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});
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while !Self::read().lserdy() {}
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}
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match clock_source {
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RtcClockSource::LSI => assert!(lsi),
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RtcClockSource::LSE => assert!(&lse.is_some()),
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_ => {}
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};
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