stm32: update configure_ls as agreed

This commit is contained in:
xoviat 2023-09-17 18:41:45 -05:00
parent daeb497045
commit a6ef314be1
8 changed files with 84 additions and 42 deletions

View File

@ -1,5 +1,5 @@
#[allow(dead_code)] #[allow(dead_code)]
#[derive(Default)] #[derive(Default, Clone, Copy)]
pub enum LseDrive { pub enum LseDrive {
#[cfg(any(rtc_v2f7, rtc_v2l4))] #[cfg(any(rtc_v2f7, rtc_v2l4))]
Low = 0, Low = 0,
@ -87,9 +87,8 @@ impl BackupDomain {
rtc_v3u5 rtc_v3u5
))] ))]
#[allow(dead_code, unused_variables)] #[allow(dead_code, unused_variables)]
pub fn configure_ls(clock_source: RtcClockSource, lse_drive: Option<LseDrive>) { pub fn configure_ls(clock_source: RtcClockSource, lsi: bool, lse: Option<LseDrive>) {
match clock_source { if lsi {
RtcClockSource::LSI => {
#[cfg(rtc_v3u5)] #[cfg(rtc_v3u5)]
let csr = crate::pac::RCC.bdcr(); let csr = crate::pac::RCC.bdcr();
@ -110,9 +109,8 @@ impl BackupDomain {
#[cfg(any(rcc_wb, rcc_wba))] #[cfg(any(rcc_wb, rcc_wba))]
while !csr.read().lsi1rdy() {} while !csr.read().lsi1rdy() {}
} }
RtcClockSource::LSE => {
let lse_drive = lse_drive.unwrap_or_default();
if let Some(lse_drive) = lse {
Self::modify(|w| { Self::modify(|w| {
#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))] #[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
w.set_lsedrv(lse_drive.into()); w.set_lsedrv(lse_drive.into());
@ -121,6 +119,10 @@ impl BackupDomain {
while !Self::read().lserdy() {} while !Self::read().lserdy() {}
} }
match clock_source {
RtcClockSource::LSI => assert!(lsi),
RtcClockSource::LSE => assert!(&lse.is_some()),
_ => {} _ => {}
}; };

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@ -291,6 +291,8 @@ pub struct Config {
pub pll: PLLConfig, pub pll: PLLConfig,
pub mux: ClockSrc, pub mux: ClockSrc,
pub rtc: Option<RtcClockSource>, pub rtc: Option<RtcClockSource>,
pub lsi: bool,
pub lse: Option<Hertz>,
pub voltage: VoltageScale, pub voltage: VoltageScale,
pub ahb_pre: AHBPrescaler, pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler, pub apb1_pre: APBPrescaler,
@ -308,6 +310,8 @@ impl Default for Config {
voltage: VoltageScale::Scale3, voltage: VoltageScale::Scale3,
mux: ClockSrc::HSI, mux: ClockSrc::HSI,
rtc: None, rtc: None,
lsi: false,
lse: None,
ahb_pre: AHBPrescaler::DIV1, ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1, apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1, apb2_pre: APBPrescaler::DIV1,
@ -421,9 +425,11 @@ pub(crate) unsafe fn init(config: Config) {
RCC.apb1enr().modify(|w| w.set_pwren(true)); RCC.apb1enr().modify(|w| w.set_pwren(true));
PWR.cr().read(); PWR.cr().read();
config BackupDomain::configure_ls(
.rtc config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
.map(|clock_source| BackupDomain::configure_ls(clock_source, None)); config.lsi,
config.lse.map(|_| Default::default()),
);
set_freqs(Clocks { set_freqs(Clocks {
sys: sys_clk, sys: sys_clk,

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@ -35,6 +35,8 @@ pub struct Config {
pub pll48: bool, pub pll48: bool,
pub rtc: Option<RtcClockSource>, pub rtc: Option<RtcClockSource>,
pub lsi: bool,
pub lse: Option<Hertz>,
} }
#[cfg(stm32f410)] #[cfg(stm32f410)]
@ -461,12 +463,15 @@ pub(crate) unsafe fn init(config: Config) {
}) })
}); });
config BackupDomain::configure_ls(
.rtc config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
.map(|clock_source| BackupDomain::configure_ls(clock_source, None)); config.lsi,
config.lse.map(|_| Default::default()),
);
let rtc = match config.rtc { let rtc = match config.rtc {
Some(RtcClockSource::LSI) => Some(LSI_FREQ), Some(RtcClockSource::LSI) => Some(LSI_FREQ),
Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
_ => None, _ => None,
}; };

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@ -138,6 +138,8 @@ pub struct Config {
#[cfg(crs)] #[cfg(crs)]
pub enable_hsi48: bool, pub enable_hsi48: bool,
pub rtc: Option<RtcClockSource>, pub rtc: Option<RtcClockSource>,
pub lse: Option<Hertz>,
pub lsi: bool,
} }
impl Default for Config { impl Default for Config {
@ -151,6 +153,8 @@ impl Default for Config {
#[cfg(crs)] #[cfg(crs)]
enable_hsi48: false, enable_hsi48: false,
rtc: None, rtc: None,
lse: None,
lsi: false,
} }
} }
} }
@ -235,9 +239,11 @@ pub(crate) unsafe fn init(config: Config) {
} }
}; };
config.rtc.map(|rtc| { BackupDomain::configure_ls(
BackupDomain::configure_ls(rtc, None); config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
}); config.lsi,
config.lse.map(|_| Default::default()),
);
RCC.cfgr().modify(|w| { RCC.cfgr().modify(|w| {
w.set_sw(sw); w.set_sw(sw);

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@ -241,6 +241,8 @@ pub struct Config {
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))] #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
pub hsi48: bool, pub hsi48: bool,
pub rtc_mux: RtcClockSource, pub rtc_mux: RtcClockSource,
pub lse: Option<Hertz>,
pub lsi: bool,
} }
impl Default for Config { impl Default for Config {
@ -255,6 +257,8 @@ impl Default for Config {
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))] #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
hsi48: false, hsi48: false,
rtc_mux: RtcClockSource::LSI, rtc_mux: RtcClockSource::LSI,
lsi: true,
lse: None,
} }
} }
} }
@ -407,7 +411,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.apb1enr1().modify(|w| w.set_pwren(true)); RCC.apb1enr1().modify(|w| w.set_pwren(true));
BackupDomain::configure_ls(config.rtc_mux, None); BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
let (sys_clk, sw) = match config.mux { let (sys_clk, sw) = match config.mux {
ClockSrc::MSI(range) => { ClockSrc::MSI(range) => {

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@ -31,6 +31,16 @@ pub use _version::*;
#[cfg(feature = "low-power")] #[cfg(feature = "low-power")]
use atomic_polyfill::{AtomicU32, Ordering}; use atomic_polyfill::{AtomicU32, Ordering};
// Model Clock Configuration
//
// pub struct Clocks {
// hse: Option<Hertz>,
// hsi: bool,
// lse: Option<Hertz>,
// lsi: bool,
// rtc: RtcSource,
// }
#[derive(Clone, Copy, Debug)] #[derive(Clone, Copy, Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct Clocks { pub struct Clocks {

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@ -108,6 +108,7 @@ pub struct Pll {
pub struct Config { pub struct Config {
pub hse: Option<Hse>, pub hse: Option<Hse>,
pub lse: Option<Hertz>, pub lse: Option<Hertz>,
pub lsi: bool,
pub sys: Sysclk, pub sys: Sysclk,
pub mux: Option<PllMux>, pub mux: Option<PllMux>,
pub pll48: Option<Pll48Source>, pub pll48: Option<Pll48Source>,
@ -136,6 +137,7 @@ pub const WPAN_DEFAULT: Config = Config {
}), }),
pll48: None, pll48: None,
rtc: Some(RtcClockSource::LSE), rtc: Some(RtcClockSource::LSE),
lsi: false,
pll: Some(Pll { pll: Some(Pll {
mul: 12, mul: 12,
@ -164,6 +166,7 @@ impl Default for Config {
pll: None, pll: None,
pllsai: None, pllsai: None,
rtc: None, rtc: None,
lsi: false,
ahb1_pre: AHBPrescaler::DIV1, ahb1_pre: AHBPrescaler::DIV1,
ahb2_pre: AHBPrescaler::DIV1, ahb2_pre: AHBPrescaler::DIV1,
@ -294,9 +297,11 @@ pub(crate) fn configure_clocks(config: &Config) {
rcc.cfgr().modify(|w| w.set_stopwuck(true)); rcc.cfgr().modify(|w| w.set_stopwuck(true));
config BackupDomain::configure_ls(
.rtc config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
.map(|clock_source| BackupDomain::configure_ls(clock_source, None)); config.lsi,
config.lse.map(|_| Default::default()),
);
match &config.hse { match &config.hse {
Some(hse) => { Some(hse) => {

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@ -138,6 +138,8 @@ pub struct Config {
pub apb1_pre: APBPrescaler, pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler, pub apb2_pre: APBPrescaler,
pub rtc_mux: RtcClockSource, pub rtc_mux: RtcClockSource,
pub lse: Option<Hertz>,
pub lsi: bool,
pub adc_clock_source: AdcClockSource, pub adc_clock_source: AdcClockSource,
} }
@ -151,6 +153,8 @@ impl Default for Config {
apb1_pre: APBPrescaler::DIV1, apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1, apb2_pre: APBPrescaler::DIV1,
rtc_mux: RtcClockSource::LSI, rtc_mux: RtcClockSource::LSI,
lsi: true,
lse: None,
adc_clock_source: AdcClockSource::default(), adc_clock_source: AdcClockSource::default(),
} }
} }
@ -231,7 +235,7 @@ pub(crate) unsafe fn init(config: Config) {
while FLASH.acr().read().latency() != ws {} while FLASH.acr().read().latency() != ws {}
// Enables the LSI if configured // Enables the LSI if configured
BackupDomain::configure_ls(config.rtc_mux, None); BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
match config.mux { match config.mux {
ClockSrc::HSI16 => { ClockSrc::HSI16 => {