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usb: make ControlPipe accept, reject async.

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This commit is contained in:
Dario Nieuwenhuis 2022-05-30 00:35:27 +02:00
parent 883e28a0fb
commit a7383840e7
3 changed files with 24 additions and 12 deletions
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20
embassy-nrf/src/usb.rs
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@ -616,6 +616,8 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a; type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a; type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a; type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
type AcceptFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
type RejectFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
fn max_packet_size(&self) -> usize { fn max_packet_size(&self) -> usize {
usize::from(self.max_packet_size) usize::from(self.max_packet_size)
@ -740,15 +742,19 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
} }
} }
fn accept(&mut self) { fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a> {
let regs = T::regs(); async move {
regs.tasks_ep0status let regs = T::regs();
.write(|w| w.tasks_ep0status().bit(true)); regs.tasks_ep0status
.write(|w| w.tasks_ep0status().bit(true));
}
} }
fn reject(&mut self) { fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a> {
let regs = T::regs(); async move {
regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true)); let regs = T::regs();
regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
}
} }
} }

10
embassy-usb/src/driver.rs
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@ -142,6 +142,12 @@ pub trait ControlPipe {
where where
Self: 'a; Self: 'a;
type DataInFuture<'a>: Future<Output = Result<(), EndpointError>> + 'a type DataInFuture<'a>: Future<Output = Result<(), EndpointError>> + 'a
where
Self: 'a;
type AcceptFuture<'a>: Future<Output = ()> + 'a
where
Self: 'a;
type RejectFuture<'a>: Future<Output = ()> + 'a
where where
Self: 'a; Self: 'a;
@ -171,12 +177,12 @@ pub trait ControlPipe {
/// Accepts a control request. /// Accepts a control request.
/// ///
/// Causes the STATUS packet for the current request to be ACKed. /// Causes the STATUS packet for the current request to be ACKed.
fn accept(&mut self); fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a>;
/// Rejects a control request. /// Rejects a control request.
/// ///
/// Sets a STALL condition on the pipe to indicate an error. /// Sets a STALL condition on the pipe to indicate an error.
fn reject(&mut self); fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a>;
} }
pub trait EndpointIn: Endpoint { pub trait EndpointIn: Endpoint {

6
embassy-usb/src/lib.rs
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@ -306,7 +306,7 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
} }
} }
} }
InResponse::Rejected => self.control.reject(), InResponse::Rejected => self.control.reject().await,
} }
} }
@ -337,8 +337,8 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
trace!(" control out data: {:02x?}", data); trace!(" control out data: {:02x?}", data);
match self.inner.handle_control_out(req, data) { match self.inner.handle_control_out(req, data) {
OutResponse::Accepted => self.control.accept(), OutResponse::Accepted => self.control.accept().await,
OutResponse::Rejected => self.control.reject(), OutResponse::Rejected => self.control.reject().await,
} }
} }
} }