usb: make ControlPipe accept, reject async.

This commit is contained in:
Dario Nieuwenhuis 2022-05-30 00:35:27 +02:00
parent 883e28a0fb
commit a7383840e7
3 changed files with 24 additions and 12 deletions

View File

@ -616,6 +616,8 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
type AcceptFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
type RejectFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
fn max_packet_size(&self) -> usize {
usize::from(self.max_packet_size)
@ -740,16 +742,20 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
}
}
fn accept(&mut self) {
fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a> {
async move {
let regs = T::regs();
regs.tasks_ep0status
.write(|w| w.tasks_ep0status().bit(true));
}
}
fn reject(&mut self) {
fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a> {
async move {
let regs = T::regs();
regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
}
}
}
fn dma_start() {

View File

@ -142,6 +142,12 @@ pub trait ControlPipe {
where
Self: 'a;
type DataInFuture<'a>: Future<Output = Result<(), EndpointError>> + 'a
where
Self: 'a;
type AcceptFuture<'a>: Future<Output = ()> + 'a
where
Self: 'a;
type RejectFuture<'a>: Future<Output = ()> + 'a
where
Self: 'a;
@ -171,12 +177,12 @@ pub trait ControlPipe {
/// Accepts a control request.
///
/// Causes the STATUS packet for the current request to be ACKed.
fn accept(&mut self);
fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a>;
/// Rejects a control request.
///
/// Sets a STALL condition on the pipe to indicate an error.
fn reject(&mut self);
fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a>;
}
pub trait EndpointIn: Endpoint {

View File

@ -306,7 +306,7 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
}
}
}
InResponse::Rejected => self.control.reject(),
InResponse::Rejected => self.control.reject().await,
}
}
@ -337,8 +337,8 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
trace!(" control out data: {:02x?}", data);
match self.inner.handle_control_out(req, data) {
OutResponse::Accepted => self.control.accept(),
OutResponse::Rejected => self.control.reject(),
OutResponse::Accepted => self.control.accept().await,
OutResponse::Rejected => self.control.reject().await,
}
}
}