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Merge pull request #1868 from MabezDev/f2-rtc-clocks

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[F2] Allow the RTC clock source to be configured with the new RTC mechanism
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xoviat 2023-09-05 23:13:57 +00:00 committed by GitHub
commit a80acf686e
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1 changed files with 36 additions and 1 deletions
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37
embassy-stm32/src/rcc/f2.rs
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@ -4,8 +4,10 @@ use core::ops::{Div, Mul};
pub use super::bus::{AHBPrescaler, APBPrescaler}; pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::pac::flash::vals::Latency; use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::{Pllp, Pllsrc, Sw}; use crate::pac::rcc::vals::{Pllp, Pllsrc, Sw};
use crate::pac::{FLASH, RCC}; use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::bd::BackupDomain;
use crate::rcc::{set_freqs, Clocks}; use crate::rcc::{set_freqs, Clocks};
use crate::rtc::RtcClockSource;
use crate::time::Hertz; use crate::time::Hertz;
/// HSI speed /// HSI speed
@ -288,6 +290,7 @@ pub struct Config {
pub pll_mux: PLLSrc, pub pll_mux: PLLSrc,
pub pll: PLLConfig, pub pll: PLLConfig,
pub mux: ClockSrc, pub mux: ClockSrc,
pub rtc: Option<RtcClockSource>,
pub voltage: VoltageScale, pub voltage: VoltageScale,
pub ahb_pre: AHBPrescaler, pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler, pub apb1_pre: APBPrescaler,
@ -304,6 +307,7 @@ impl Default for Config {
pll: PLLConfig::default(), pll: PLLConfig::default(),
voltage: VoltageScale::Scale3, voltage: VoltageScale::Scale3,
mux: ClockSrc::HSI, mux: ClockSrc::HSI,
rtc: None,
ahb_pre: AHBPrescaler::NotDivided, ahb_pre: AHBPrescaler::NotDivided,
apb1_pre: APBPrescaler::NotDivided, apb1_pre: APBPrescaler::NotDivided,
apb2_pre: APBPrescaler::NotDivided, apb2_pre: APBPrescaler::NotDivided,
@ -414,6 +418,37 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().modify(|w| w.set_hsion(false)); RCC.cr().modify(|w| w.set_hsion(false));
} }
RCC.apb1enr().modify(|w| w.set_pwren(true));
PWR.cr().read();
match config.rtc {
Some(RtcClockSource::LSE) => {
// 1. Unlock the backup domain
PWR.cr().modify(|w| w.set_dbp(true));
// 2. Setup the LSE
RCC.bdcr().modify(|w| {
// Enable LSE
w.set_lseon(true);
});
// Wait until LSE is running
while !RCC.bdcr().read().lserdy() {}
BackupDomain::set_rtc_clock_source(RtcClockSource::LSE);
}
Some(RtcClockSource::LSI) => {
// Turn on the internal 32 kHz LSI oscillator
RCC.csr().modify(|w| w.set_lsion(true));
// Wait until LSI is running
while !RCC.csr().read().lsirdy() {}
BackupDomain::set_rtc_clock_source(RtcClockSource::LSI);
}
_ => todo!(),
}
set_freqs(Clocks { set_freqs(Clocks {
sys: sys_clk, sys: sys_clk,
ahb1: ahb_freq, ahb1: ahb_freq,