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Run rustfmt.

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This commit is contained in:
Dario Nieuwenhuis
2022-06-12 22:15:44 +02:00
parent 6199bdea71
commit a8703b7598
340 changed files with 1326 additions and 3020 deletions
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47
embassy-stm32/build.rs
View File

@ -1,10 +1,10 @@
use std::collections::{HashMap, HashSet};
use std::fmt::Write as _;
use std::path::PathBuf;
use std::{env, fs};
use proc_macro2::TokenStream;
use quote::{format_ident, quote};
use std::collections::{HashMap, HashSet};
use std::env;
use std::fmt::Write as _;
use std::fs;
use std::path::PathBuf;
use stm32_metapac::metadata::METADATA;
fn main() {
@ -116,10 +116,7 @@ fn main() {
continue;
}
for irq in p.interrupts {
dma_irqs
.entry(irq.interrupt)
.or_default()
.push((p.name, irq.signal));
dma_irqs.entry(irq.interrupt).or_default().push((p.name, irq.signal));
}
}
}
@ -128,9 +125,7 @@ fn main() {
for (irq, channels) in dma_irqs {
let irq = format_ident!("{}", irq);
let channels = channels
.iter()
.map(|(dma, ch)| format_ident!("{}_{}", dma, ch));
let channels = channels.iter().map(|(dma, ch)| format_ident!("{}_{}", dma, ch));
g.extend(quote! {
#[crate::interrupt]
@ -147,9 +142,7 @@ fn main() {
for p in METADATA.peripherals {
// generating RccPeripheral impl for H7 ADC3 would result in bad frequency
if !singletons.contains(&p.name.to_string())
|| (p.name == "ADC3" && METADATA.line.starts_with("STM32H7"))
{
if !singletons.contains(&p.name.to_string()) || (p.name == "ADC3" && METADATA.line.starts_with("STM32H7")) {
continue;
}
@ -568,12 +561,7 @@ fn main() {
let mut pins_table: Vec<Vec<String>> = Vec::new();
let mut dma_channels_table: Vec<Vec<String>> = Vec::new();
let gpio_base = METADATA
.peripherals
.iter()
.find(|p| p.name == "GPIOA")
.unwrap()
.address as u32;
let gpio_base = METADATA.peripherals.iter().find(|p| p.name == "GPIOA").unwrap().address as u32;
let gpio_stride = 0x400;
for p in METADATA.peripherals {
@ -618,11 +606,7 @@ fn main() {
for ch in METADATA.dma_channels {
let mut row = Vec::new();
let dma_peri = METADATA
.peripherals
.iter()
.find(|p| p.name == ch.dma)
.unwrap();
let dma_peri = METADATA.peripherals.iter().find(|p| p.name == ch.dma).unwrap();
let bi = dma_peri.registers.as_ref().unwrap();
let num;
@ -649,10 +633,7 @@ fn main() {
row.push(num.to_string());
if let Some(dmamux) = &ch.dmamux {
let dmamux_channel = ch.dmamux_channel.unwrap();
row.push(format!(
"{{dmamux: {}, dmamux_channel: {}}}",
dmamux, dmamux_channel
));
row.push(format!("{{dmamux: {}, dmamux_channel: {}}}", dmamux, dmamux_channel));
} else {
row.push("{}".to_string());
}
@ -709,11 +690,7 @@ fn main() {
};
if let Some(core) = core_name {
println!(
"cargo:rustc-cfg={}_{}",
&chip_name[..chip_name.len() - 2],
core
);
println!("cargo:rustc-cfg={}_{}", &chip_name[..chip_name.len() - 2], core);
} else {
println!("cargo:rustc-cfg={}", &chip_name[..chip_name.len() - 2]);
}

8
embassy-stm32/src/adc/f1.rs
View File

@ -1,10 +1,12 @@
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use embedded_hal_02::blocking::delay::DelayUs;
use crate::adc::{AdcPin, Instance};
use crate::rcc::get_freqs;
use crate::time::Hertz;
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use embedded_hal_02::blocking::delay::DelayUs;
pub const VDDA_CALIB_MV: u32 = 3300;
pub const ADC_MAX: u32 = (1 << 12) - 1;

20
embassy-stm32/src/adc/v2.rs
View File

@ -1,9 +1,11 @@
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use embedded_hal_02::blocking::delay::DelayUs;
use crate::adc::{AdcPin, Instance};
use crate::time::Hertz;
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use embedded_hal_02::blocking::delay::DelayUs;
pub const VDDA_CALIB_MV: u32 = 3000;
@ -132,9 +134,7 @@ impl Prescaler {
2..=3 => Self::Div4,
4..=5 => Self::Div6,
6..=7 => Self::Div8,
_ => panic!(
"Selected PCLK2 frequency is too high for ADC with largest possible prescaler."
),
_ => panic!("Selected PCLK2 frequency is too high for ADC with largest possible prescaler."),
}
}
@ -165,9 +165,7 @@ where
let presc = unsafe { Prescaler::from_pclk2(crate::rcc::get_freqs().apb2) };
unsafe {
T::common_regs()
.ccr()
.modify(|w| w.set_adcpre(presc.adcpre()));
T::common_regs().ccr().modify(|w| w.set_adcpre(presc.adcpre()));
}
unsafe {
@ -241,9 +239,7 @@ where
pin.set_as_analog();
// Configure ADC
T::regs()
.cr1()
.modify(|reg| reg.set_res(self.resolution.res()));
T::regs().cr1().modify(|reg| reg.set_res(self.resolution.res()));
// Select channel
T::regs().sqr3().write(|reg| reg.set_sq(0, pin.channel()));

22
embassy-stm32/src/adc/v3.rs
View File

@ -1,9 +1,11 @@
use crate::adc::{AdcPin, Instance};
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use embedded_hal_02::blocking::delay::DelayUs;
use crate::adc::{AdcPin, Instance};
use crate::Unborrow;
pub const VDDA_CALIB_MV: u32 = 3000;
/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
@ -369,13 +371,9 @@ impl<'d, T: Instance> Adc<'d, T> {
// Configure ADC
#[cfg(not(stm32g0))]
T::regs()
.cfgr()
.modify(|reg| reg.set_res(self.resolution.res()));
T::regs().cfgr().modify(|reg| reg.set_res(self.resolution.res()));
#[cfg(stm32g0)]
T::regs()
.cfgr1()
.modify(|reg| reg.set_res(self.resolution.res()));
T::regs().cfgr1().modify(|reg| reg.set_res(self.resolution.res()));
// Configure channel
Self::set_channel_sample_time(pin.channel(), self.sample_time);
@ -384,9 +382,7 @@ impl<'d, T: Instance> Adc<'d, T> {
#[cfg(not(stm32g0))]
T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
#[cfg(stm32g0)]
T::regs()
.chselr()
.write(|reg| reg.set_chsel(pin.channel() as u32));
T::regs().chselr().write(|reg| reg.set_chsel(pin.channel() as u32));
// Some models are affected by an erratum:
// If we perform conversions slower than 1 kHz, the first read ADC value can be
@ -407,9 +403,7 @@ impl<'d, T: Instance> Adc<'d, T> {
#[cfg(stm32g0)]
unsafe fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
T::regs()
.smpr()
.modify(|reg| reg.set_smp1(sample_time.sample_time()));
T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.sample_time()));
}
#[cfg(not(stm32g0))]

17
embassy-stm32/src/adc/v4.rs
View File

@ -1,16 +1,13 @@
use core::marker::PhantomData;
use crate::time::{Hertz, U32Ext};
use crate::Unborrow;
use atomic_polyfill::AtomicU8;
use atomic_polyfill::Ordering;
use atomic_polyfill::{AtomicU8, Ordering};
use embedded_hal_02::blocking::delay::DelayUs;
use pac::adc::vals::{Adcaldif, Boost, Difsel, Exten, Pcsel};
use pac::adccommon::vals::Presc;
use crate::pac;
use super::{AdcPin, Instance};
use crate::time::{Hertz, U32Ext};
use crate::{pac, Unborrow};
pub enum Resolution {
SixteenBit,
@ -333,9 +330,7 @@ impl<'d, T: Instance + crate::rcc::RccPeripheral> Adc<'d, T> {
let prescaler = Prescaler::from_ker_ck(T::frequency());
unsafe {
T::common_regs()
.ccr()
.modify(|w| w.set_presc(prescaler.presc()));
T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
}
let frequency = Hertz(T::frequency().0 / prescaler.divisor());
@ -509,9 +504,7 @@ impl<'d, T: Instance + crate::rcc::RccPeripheral> Adc<'d, T> {
unsafe fn read_channel(&mut self, channel: u8) -> u16 {
// Configure ADC
T::regs()
.cfgr()
.modify(|reg| reg.set_res(self.resolution.res()));
T::regs().cfgr().modify(|reg| reg.set_res(self.resolution.res()));
// Configure channel
Self::set_channel_sample_time(channel, self.sample_time);

7
embassy-stm32/src/can/bxcan.rs
View File

@ -1,13 +1,12 @@
use core::marker::PhantomData;
use core::ops::{Deref, DerefMut};
use crate::Unborrow;
pub use bxcan;
use embassy_hal_common::unborrow;
use crate::gpio::sealed::AFType;
use crate::{peripherals, rcc::RccPeripheral};
pub use bxcan;
use crate::rcc::RccPeripheral;
use crate::{peripherals, Unborrow};
pub struct Can<'d, T: Instance + bxcan::Instance> {
phantom: PhantomData<&'d mut T>,

3
embassy-stm32/src/crc/v1.rs
View File

@ -1,10 +1,11 @@
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use crate::pac::CRC as PAC_CRC;
use crate::peripherals::CRC;
use crate::rcc::sealed::RccPeripheral;
use crate::Unborrow;
use embassy_hal_common::unborrow;
pub struct Crc<'d> {
_peripheral: CRC,

3
embassy-stm32/src/crc/v2v3.rs
View File

@ -1,11 +1,12 @@
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use crate::pac::crc::vals;
use crate::pac::CRC as PAC_CRC;
use crate::peripherals::CRC;
use crate::rcc::sealed::RccPeripheral;
use crate::Unborrow;
use embassy_hal_common::unborrow;
pub struct Crc<'d> {
_peripheral: CRC,

3
embassy-stm32/src/dac/mod.rs
View File

@ -3,9 +3,10 @@
#[cfg_attr(dac_v1, path = "v1.rs")]
#[cfg_attr(dac_v2, path = "v2.rs")]
mod _version;
use crate::peripherals;
pub use _version::*;
use crate::peripherals;
pub(crate) mod sealed {
pub trait Instance {
fn regs() -> &'static crate::pac::dac::Dac;

23
embassy-stm32/src/dac/v2.rs
View File

@ -1,8 +1,10 @@
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use crate::dac::{DacPin, Instance};
use crate::pac::dac;
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@ -93,23 +95,14 @@ pub struct Dac<'d, T: Instance> {
macro_rules! enable {
($enable_reg:ident, $enable_field:ident, $reset_reg:ident, $reset_field:ident) => {
crate::pac::RCC
.$enable_reg()
.modify(|w| w.$enable_field(true));
crate::pac::RCC
.$reset_reg()
.modify(|w| w.$reset_field(true));
crate::pac::RCC
.$reset_reg()
.modify(|w| w.$reset_field(false));
crate::pac::RCC.$enable_reg().modify(|w| w.$enable_field(true));
crate::pac::RCC.$reset_reg().modify(|w| w.$reset_field(true));
crate::pac::RCC.$reset_reg().modify(|w| w.$reset_field(false));
};
}
impl<'d, T: Instance> Dac<'d, T> {
pub fn new_1ch(
peri: impl Unborrow<Target = T> + 'd,
_ch1: impl Unborrow<Target = impl DacPin<T, 1>> + 'd,
) -> Self {
pub fn new_1ch(peri: impl Unborrow<Target = T> + 'd, _ch1: impl Unborrow<Target = impl DacPin<T, 1>> + 'd) -> Self {
unborrow!(peri);
Self::new_inner(peri, 1)
}

16
embassy-stm32/src/dcmi.rs
View File

@ -1,13 +1,14 @@
use core::marker::PhantomData;
use core::task::Poll;
use crate::interrupt::{Interrupt, InterruptExt};
use crate::Unborrow;
use embassy::waitqueue::AtomicWaker;
use embassy_hal_common::unborrow;
use futures::future::poll_fn;
use crate::gpio::{sealed::AFType, Speed};
use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
use crate::interrupt::{Interrupt, InterruptExt};
use crate::Unborrow;
/// The level on the VSync pin when the data is not valid on the parallel interface.
#[derive(Clone, Copy, PartialEq)]
@ -466,14 +467,7 @@ where
let src = r.dr().ptr() as *mut u32;
unsafe {
channel.start_double_buffered_read(
request,
src,
m0ar,
m1ar,
chunk_size,
TransferOptions::default(),
);
channel.start_double_buffered_read(request, src, m0ar, m1ar, chunk_size, TransferOptions::default());
}
let mut last_chunk_set_for_transfer = false;

25
embassy-stm32/src/dma/bdma.rs
View File

@ -3,16 +3,15 @@
use core::sync::atomic::{fence, Ordering};
use core::task::Waker;
use crate::interrupt::{Interrupt, InterruptExt};
use embassy::waitqueue::AtomicWaker;
use super::{TransferOptions, Word, WordSize};
use crate::_generated::BDMA_CHANNEL_COUNT;
use crate::dma::Request;
use crate::interrupt::{Interrupt, InterruptExt};
use crate::pac;
use crate::pac::bdma::vals;
use super::{TransferOptions, Word, WordSize};
impl From<WordSize> for vals::Size {
fn from(raw: WordSize) -> Self {
match raw {
@ -185,14 +184,8 @@ mod low_level_api {
#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
#[cfg(dmamux)] dmamux_ch_num: u8,
) {
assert!(
options.mburst == crate::dma::Burst::Single,
"Burst mode not supported"
);
assert!(
options.pburst == crate::dma::Burst::Single,
"Burst mode not supported"
);
assert!(options.mburst == crate::dma::Burst::Single, "Burst mode not supported");
assert!(options.pburst == crate::dma::Burst::Single, "Burst mode not supported");
assert!(
options.flow_ctrl == crate::dma::FlowControl::Dma,
"Peripheral flow control not supported"
@ -206,10 +199,7 @@ mod low_level_api {
super::super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
#[cfg(bdma_v2)]
critical_section::with(|_| {
dma.cselr()
.modify(|w| w.set_cs(channel_number as _, request))
});
critical_section::with(|_| dma.cselr().modify(|w| w.set_cs(channel_number as _, request)));
// "Preceding reads and writes cannot be moved past subsequent writes."
fence(Ordering::SeqCst);
@ -279,10 +269,7 @@ mod low_level_api {
let cr = dma.ch(channel_num).cr();
if isr.teif(channel_num) {
panic!(
"DMA: error on BDMA@{:08x} channel {}",
dma.0 as u32, channel_num
);
panic!("DMA: error on BDMA@{:08x} channel {}", dma.0 as u32, channel_num);
}
if isr.tcif(channel_num) && cr.read().tcie() {
cr.write(|_| ()); // Disable channel interrupts with the default value.

18
embassy-stm32/src/dma/dma.rs
View File

@ -1,15 +1,13 @@
use core::sync::atomic::{fence, Ordering};
use core::task::Waker;
use crate::interrupt::{Interrupt, InterruptExt};
use embassy::waitqueue::AtomicWaker;
use crate::_generated::DMA_CHANNEL_COUNT;
use crate::interrupt;
use crate::pac;
use crate::pac::dma::{regs, vals};
use super::{Burst, FlowControl, Request, TransferOptions, Word, WordSize};
use crate::_generated::DMA_CHANNEL_COUNT;
use crate::interrupt::{Interrupt, InterruptExt};
use crate::pac::dma::{regs, vals};
use crate::{interrupt, pac};
impl From<WordSize> for vals::Size {
fn from(raw: WordSize) -> Self {
@ -407,10 +405,7 @@ mod low_level_api {
let isr = dma.isr(channel_num / 4).read();
if isr.teif(channel_num % 4) {
panic!(
"DMA: error on DMA@{:08x} channel {}",
dma.0 as u32, channel_num
);
panic!("DMA: error on DMA@{:08x} channel {}", dma.0 as u32, channel_num);
}
if isr.tcif(channel_num % 4) && cr.read().tcie() {
@ -418,8 +413,7 @@ mod low_level_api {
cr.write(|_| ()); // Disable channel with the default value.
} else {
// for double buffered mode, clear TCIF flag but do not stop the transfer
dma.ifcr(channel_num / 4)
.write(|w| w.set_tcif(channel_num % 4, true));
dma.ifcr(channel_num / 4).write(|w| w.set_tcif(channel_num % 4, true));
}
STATE.channels[state_index].waker.wake();
}

9
embassy-stm32/src/dma/dmamux.rs
View File

@ -1,13 +1,8 @@
#![macro_use]
use crate::pac;
use crate::peripherals;
use crate::{pac, peripherals};
pub(crate) unsafe fn configure_dmamux(
dmamux_regs: pac::dmamux::Dmamux,
dmamux_ch_num: u8,
request: u8,
) {
pub(crate) unsafe fn configure_dmamux(dmamux_regs: pac::dmamux::Dmamux, dmamux_ch_num: u8, request: u8) {
let ch_mux_regs = dmamux_regs.ccr(dmamux_ch_num as _);
ch_mux_regs.write(|reg| {
reg.set_nbreq(0);

10
embassy-stm32/src/dma/gpdma.rs
View File

@ -1,15 +1,13 @@
use core::sync::atomic::{fence, Ordering};
use core::task::Waker;
use crate::interrupt::{Interrupt, InterruptExt};
use embassy::waitqueue::AtomicWaker;
use crate::_generated::GPDMA_CHANNEL_COUNT;
use crate::interrupt;
use crate::pac;
use crate::pac::gpdma::{vals, Gpdma};
use super::{Request, TransferOptions, Word, WordSize};
use crate::_generated::GPDMA_CHANNEL_COUNT;
use crate::interrupt::{Interrupt, InterruptExt};
use crate::pac::gpdma::{vals, Gpdma};
use crate::{interrupt, pac};
impl From<WordSize> for vals::ChTr1Dw {
fn from(raw: WordSize) -> Self {

22
embassy-stm32/src/dma/mod.rs
View File

@ -7,18 +7,18 @@ mod dmamux;
#[cfg(gpdma)]
mod gpdma;
#[cfg(dmamux)]
pub use dmamux::*;
use crate::Unborrow;
use core::future::Future;
use core::marker::PhantomData;
use core::mem;
use core::pin::Pin;
use core::task::Waker;
use core::task::{Context, Poll};
use core::task::{Context, Poll, Waker};
#[cfg(dmamux)]
pub use dmamux::*;
use embassy_hal_common::unborrow;
use crate::Unborrow;
#[cfg(feature = "unstable-pac")]
pub mod low_level {
pub use super::transfers::*;
@ -249,15 +249,7 @@ mod transfers {
) -> impl Future<Output = ()> + 'a {
unborrow!(channel);
unsafe {
channel.start_write_repeated::<W>(
request,
repeated,
count,
reg_addr,
Default::default(),
)
};
unsafe { channel.start_write_repeated::<W>(request, repeated, count, reg_addr, Default::default()) };
Transfer::new(channel)
}

5
embassy-stm32/src/eth/generic_smi.rs
View File

@ -51,10 +51,7 @@ unsafe impl PHY for GenericSMI {
Self::smi_write_ext(sm, PHY_REG_WUCSR, 0);
// Enable auto-negotiation
sm.smi_write(
PHY_REG_BCR,
PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M,
);
sm.smi_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M);
}
fn poll_link<S: StationManagement>(sm: &mut S) -> bool {

25
embassy-stm32/src/eth/v1/mod.rs
View File

@ -4,33 +4,30 @@ use core::marker::PhantomData;
use core::sync::atomic::{fence, Ordering};
use core::task::Waker;
use crate::Unborrow;
use embassy::waitqueue::AtomicWaker;
use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
use embassy_hal_common::unborrow;
use embassy_net::{Device, DeviceCapabilities, LinkState, PacketBuf, MTU};
use crate::gpio::sealed::Pin as __GpioPin;
use crate::gpio::{sealed::AFType, AnyPin, Speed};
use crate::gpio::sealed::{AFType, Pin as __GpioPin};
use crate::gpio::{AnyPin, Speed};
#[cfg(eth_v1a)]
use crate::pac::AFIO;
#[cfg(any(eth_v1b, eth_v1c))]
use crate::pac::SYSCFG;
use crate::pac::{ETH, RCC};
use crate::Unborrow;
mod descriptors;
mod rx_desc;
mod tx_desc;
use super::*;
use descriptors::DescriptorRing;
use stm32_metapac::eth::vals::{
Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf,
};
use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
pub struct State<'d, T: Instance, const TX: usize, const RX: usize>(
StateStorage<Inner<'d, T, TX, RX>>,
);
use super::*;
pub struct State<'d, T: Instance, const TX: usize, const RX: usize>(StateStorage<Inner<'d, T, TX, RX>>);
impl<'d, T: Instance, const TX: usize, const RX: usize> State<'d, T, TX, RX> {
pub fn new() -> Self {
Self(StateStorage::new())
@ -300,9 +297,7 @@ unsafe impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> StationMa
}
}
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device
for Ethernet<'d, T, P, TX, RX>
{
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device for Ethernet<'d, T, P, TX, RX> {
fn is_transmit_ready(&mut self) -> bool {
self.state.with(|s| s.desc_ring.tx.available())
}
@ -339,9 +334,7 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device
}
}
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop
for Ethernet<'d, T, P, TX, RX>
{
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop for Ethernet<'d, T, P, TX, RX> {
fn drop(&mut self) {
// NOTE(unsafe) We have `&mut self` and the interrupt doesn't use this registers
unsafe {

12
embassy-stm32/src/eth/v1/rx_desc.rs
View File

@ -59,8 +59,7 @@ impl RDes {
//
// Contains first buffer of packet AND contains last buf of
// packet AND no errors
(self.rdes0.get() & (RXDESC_0_ES | RXDESC_0_FS | RXDESC_0_LS))
== (RXDESC_0_FS | RXDESC_0_LS)
(self.rdes0.get() & (RXDESC_0_ES | RXDESC_0_FS | RXDESC_0_LS)) == (RXDESC_0_FS | RXDESC_0_LS)
}
/// Return true if this RDes is not currently owned by the DMA
@ -72,8 +71,7 @@ impl RDes {
/// Configures the reception buffer address and length and passed descriptor ownership to the DMA
#[inline(always)]
pub fn set_ready(&mut self, buf_addr: u32, buf_len: usize) {
self.rdes1
.set(self.rdes1.get() | (buf_len as u32) & RXDESC_1_RBS_MASK);
self.rdes1.set(self.rdes1.get() | (buf_len as u32) & RXDESC_1_RBS_MASK);
self.rdes2.set(buf_addr);
// "Preceding reads and writes cannot be moved past subsequent writes."
@ -220,11 +218,7 @@ impl<const N: usize> RDesRing<N> {
// We already have fences in `set_owned`, which is called in `setup`
// Start receive
unsafe {
ETH.ethernet_dma()
.dmaomr()
.modify(|w| w.set_sr(DmaomrSr::STARTED))
};
unsafe { ETH.ethernet_dma().dmaomr().modify(|w| w.set_sr(DmaomrSr::STARTED)) };
self.demand_poll();
}

9
embassy-stm32/src/eth/v1/tx_desc.rs
View File

@ -100,8 +100,7 @@ impl TDes {
// set up as a part fo the ring buffer - configures the tdes
pub fn setup(&mut self, next: Option<&Self>) {
// Defer this initialization to this function, so we can have `RingEntry` on bss.
self.tdes0
.set(TXDESC_0_TCH | TXDESC_0_IOC | TXDESC_0_FS | TXDESC_0_LS);
self.tdes0.set(TXDESC_0_TCH | TXDESC_0_IOC | TXDESC_0_FS | TXDESC_0_LS);
match next {
Some(next) => self.set_buffer2(next as *const TDes as *const u8),
None => {
@ -169,11 +168,7 @@ impl<const N: usize> TDesRing<N> {
// volatiles
// Start transmission
unsafe {
ETH.ethernet_dma()
.dmaomr()
.modify(|w| w.set_st(St::STARTED))
};
unsafe { ETH.ethernet_dma().dmaomr().modify(|w| w.set_st(St::STARTED)) };
}
/// Return true if a TDes is available for use

12
embassy-stm32/src/eth/v2/descriptors.rs
View File

@ -101,11 +101,9 @@ impl<const N: usize> TDesRing<N> {
unsafe {
let dma = ETH.ethernet_dma();
dma.dmactx_dlar()
.write(|w| w.0 = &self.td as *const _ as u32);
dma.dmactx_dlar().write(|w| w.0 = &self.td as *const _ as u32);
dma.dmactx_rlr().write(|w| w.set_tdrl((N as u16) - 1));
dma.dmactx_dtpr()
.write(|w| w.0 = &self.td[0] as *const _ as u32);
dma.dmactx_dtpr().write(|w| w.0 = &self.td[0] as *const _ as u32);
}
}
@ -127,8 +125,7 @@ impl<const N: usize> TDesRing<N> {
// Read format
td.tdes0.set(address);
td.tdes2
.set(pkt_len as u32 & EMAC_TDES2_B1L | EMAC_TDES2_IOC);
td.tdes2.set(pkt_len as u32 & EMAC_TDES2_B1L | EMAC_TDES2_IOC);
// FD: Contains first buffer of packet
// LD: Contains last buffer of packet
@ -225,8 +222,7 @@ impl RDes {
#[inline(always)]
pub fn set_ready(&mut self, buf_addr: u32) {
self.rdes0.set(buf_addr);
self.rdes3
.set(EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN);
self.rdes3.set(EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN);
}
}

21
embassy-stm32/src/eth/v2/mod.rs
View File

@ -2,23 +2,22 @@ use core::marker::PhantomData;
use core::sync::atomic::{fence, Ordering};
use core::task::Waker;
use crate::Unborrow;
use embassy::waitqueue::AtomicWaker;
use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
use embassy_hal_common::unborrow;
use embassy_net::{Device, DeviceCapabilities, LinkState, PacketBuf, MTU};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{sealed::AFType, AnyPin, Speed};
use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::{AnyPin, Speed};
use crate::pac::{ETH, RCC, SYSCFG};
use crate::Unborrow;
mod descriptors;
use super::*;
use descriptors::DescriptorRing;
pub struct State<'d, T: Instance, const TX: usize, const RX: usize>(
StateStorage<Inner<'d, T, TX, RX>>,
);
use super::*;
pub struct State<'d, T: Instance, const TX: usize, const RX: usize>(StateStorage<Inner<'d, T, TX, RX>>);
impl<'d, T: Instance, const TX: usize, const RX: usize> State<'d, T, TX, RX> {
pub fn new() -> Self {
Self(StateStorage::new())
@ -234,9 +233,7 @@ unsafe impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> StationMa
}
}
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device
for Ethernet<'d, T, P, TX, RX>
{
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device for Ethernet<'d, T, P, TX, RX> {
fn is_transmit_ready(&mut self) -> bool {
self.state.with(|s| s.desc_ring.tx.available())
}
@ -273,9 +270,7 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device
}
}
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop
for Ethernet<'d, T, P, TX, RX>
{
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop for Ethernet<'d, T, P, TX, RX> {
fn drop(&mut self) {
// NOTE(unsafe) We have `&mut self` and the interrupt doesn't use this registers
unsafe {

19
embassy-stm32/src/exti.rs
View File

@ -1,17 +1,15 @@
use crate::Unborrow;
use core::future::Future;
use core::marker::PhantomData;
use core::pin::Pin;
use core::task::{Context, Poll};
use embassy::waitqueue::AtomicWaker;
use embassy_hal_common::unsafe_impl_unborrow;
use crate::gpio::{AnyPin, Input, Pin as GpioPin};
use crate::interrupt;
use crate::pac;
use crate::pac::exti::regs::Lines;
use crate::pac::EXTI;
use crate::peripherals;
use crate::{interrupt, pac, peripherals, Unborrow};
const EXTI_COUNT: usize = 16;
const NEW_AW: AtomicWaker = AtomicWaker::new();
@ -130,9 +128,10 @@ impl<'d, T: GpioPin> ExtiInput<'d, T> {
}
mod eh02 {
use super::*;
use core::convert::Infallible;
use super::*;
impl<'d, T: GpioPin> embedded_hal_02::digital::v2::InputPin for ExtiInput<'d, T> {
type Error = Infallible;
@ -148,9 +147,10 @@ mod eh02 {
#[cfg(feature = "unstable-traits")]
mod eh1 {
use super::*;
use core::convert::Infallible;
use super::*;
impl<'d, T: GpioPin> embedded_hal_1::digital::ErrorType for ExtiInput<'d, T> {
type Error = Infallible;
}
@ -212,9 +212,7 @@ impl<'a> ExtiInputFuture<'a> {
fn new(pin: u8, port: u8, rising: bool, falling: bool) -> Self {
critical_section::with(|_| unsafe {
let pin = pin as usize;
exticr_regs()
.exticr(pin / 4)
.modify(|w| w.set_exti(pin % 4, port));
exticr_regs().exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port));
EXTI.rtsr(0).modify(|w| w.set_line(pin, rising));
EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
@ -366,8 +364,7 @@ macro_rules! enable_irq {
/// safety: must be called only once
pub(crate) unsafe fn init() {
use crate::interrupt::Interrupt;
use crate::interrupt::InterruptExt;
use crate::interrupt::{Interrupt, InterruptExt};
foreach_exti_irq!(enable_irq);

5
embassy-stm32/src/flash/f3.rs
View File

@ -20,10 +20,7 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
let mut ret: Result<(), Error> = Ok(());
let mut offset = offset;
for chunk in buf.chunks(2) {
write_volatile(
offset as *mut u16,
u16::from_le_bytes(chunk[0..2].try_into().unwrap()),
);
write_volatile(offset as *mut u16, u16::from_le_bytes(chunk[0..2].try_into().unwrap()));
offset += chunk.len() as u32;
ret = blocking_wait_ready();

5
embassy-stm32/src/flash/f7.rs
View File

@ -26,10 +26,7 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
let mut offset = offset;
for chunk in buf.chunks(super::WRITE_SIZE) {
for val in chunk.chunks(4) {
write_volatile(
offset as *mut u32,
u32::from_le_bytes(val[0..4].try_into().unwrap()),
);
write_volatile(offset as *mut u32, u32::from_le_bytes(val[0..4].try_into().unwrap()));
offset += val.len() as u32;
// prevents parallelism errors

8
embassy-stm32/src/flash/h7.rs
View File

@ -28,8 +28,7 @@ pub(crate) unsafe fn unlock() {
}
pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error> {
let bank = if !is_dual_bank() || (offset - super::FLASH_BASE as u32) < SECOND_BANK_OFFSET as u32
{
let bank = if !is_dual_bank() || (offset - super::FLASH_BASE as u32) < SECOND_BANK_OFFSET as u32 {
pac::FLASH.bank(0)
} else {
pac::FLASH.bank(1)
@ -46,10 +45,7 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
'outer: for chunk in buf.chunks(super::WRITE_SIZE) {
for val in chunk.chunks(4) {
trace!("Writing at {:x}", offset);
write_volatile(
offset as *mut u32,
u32::from_le_bytes(val[0..4].try_into().unwrap()),
);
write_volatile(offset as *mut u32, u32::from_le_bytes(val[0..4].try_into().unwrap()));
offset += val.len() as u32;
ret = blocking_wait_ready(bank);

11
embassy-stm32/src/flash/l.rs
View File

@ -42,10 +42,7 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
let mut offset = offset;
for chunk in buf.chunks(super::WRITE_SIZE) {
for val in chunk.chunks(4) {
write_volatile(
offset as *mut u32,
u32::from_le_bytes(val[0..4].try_into().unwrap()),
);
write_volatile(offset as *mut u32, u32::from_le_bytes(val[0..4].try_into().unwrap()));
offset += val.len() as u32;
}
@ -80,11 +77,7 @@ pub(crate) unsafe fn blocking_erase(from: u32, to: u32) -> Result<(), Error> {
let idx = (page - super::FLASH_BASE as u32) / super::ERASE_SIZE as u32;
#[cfg(flash_l4)]
let (idx, bank) = if idx > 255 {
(idx - 256, true)
} else {
(idx, false)
};
let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
pac::FLASH.cr().modify(|w| {
w.set_per(true);

18
embassy-stm32/src/flash/mod.rs
View File

@ -1,17 +1,11 @@
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use embedded_storage::nor_flash::{ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash};
pub use crate::pac::{ERASE_SIZE, ERASE_VALUE, FLASH_BASE, FLASH_SIZE, WRITE_SIZE};
use crate::peripherals::FLASH;
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use embedded_storage::nor_flash::{
ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash,
};
pub use crate::pac::ERASE_SIZE;
pub use crate::pac::ERASE_VALUE;
pub use crate::pac::FLASH_BASE;
pub use crate::pac::FLASH_SIZE;
pub use crate::pac::WRITE_SIZE;
const FLASH_END: usize = FLASH_BASE + FLASH_SIZE;
#[cfg_attr(any(flash_wl, flash_wb, flash_l0, flash_l1, flash_l4), path = "l.rs")]

3
embassy-stm32/src/fmc/mod.rs
View File

@ -1,9 +1,10 @@
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use crate::gpio::sealed::AFType;
use crate::gpio::{Pull, Speed};
use crate::Unborrow;
mod pins;
pub use pins::*;

50
embassy-stm32/src/gpio.rs
View File

@ -1,12 +1,11 @@
#![macro_use]
use crate::Unborrow;
use core::convert::Infallible;
use core::marker::PhantomData;
use embassy_hal_common::{unborrow, unsafe_impl_unborrow};
use crate::pac;
use crate::pac::gpio::{self, vals};
use crate::peripherals;
use crate::{pac, peripherals, Unborrow};
/// Pull setting for an input.
#[derive(Debug, Eq, PartialEq)]
@ -138,8 +137,7 @@ impl<'d, T: Pin> Drop for Input<'d, T> {
#[cfg(gpio_v1)]
{
let crlh = if n < 8 { 0 } else { 1 };
r.cr(crlh)
.modify(|w| w.set_cnf_in(n % 8, vals::CnfIn::FLOATING));
r.cr(crlh).modify(|w| w.set_cnf_in(n % 8, vals::CnfIn::FLOATING));
}
#[cfg(gpio_v2)]
r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
@ -264,12 +262,7 @@ pub struct OutputOpenDrain<'d, T: Pin> {
impl<'d, T: Pin> OutputOpenDrain<'d, T> {
#[inline]
pub fn new(
pin: impl Unborrow<Target = T> + 'd,
initial_output: Level,
speed: Speed,
pull: Pull,
) -> Self {
pub fn new(pin: impl Unborrow<Target = T> + 'd, initial_output: Level, speed: Speed, pull: Pull) -> Self {
unborrow!(pin);
match initial_output {
@ -289,8 +282,7 @@ impl<'d, T: Pin> OutputOpenDrain<'d, T> {
Pull::None => {}
}
r.cr(crlh).modify(|w| w.set_mode(n % 8, speed.into()));
r.cr(crlh)
.modify(|w| w.set_cnf_out(n % 8, vals::CnfOut::OPENDRAIN));
r.cr(crlh).modify(|w| w.set_cnf_out(n % 8, vals::CnfOut::OPENDRAIN));
}
#[cfg(gpio_v2)]
{
@ -480,18 +472,12 @@ pub(crate) mod sealed {
block.afr(pin / 8).modify(|w| w.set_afr(pin % 8, af_num));
match af_type {
AFType::Input => {}
AFType::OutputPushPull => {
block.otyper().modify(|w| w.set_ot(pin, vals::Ot::PUSHPULL))
}
AFType::OutputOpenDrain => block
.otyper()
.modify(|w| w.set_ot(pin, vals::Ot::OPENDRAIN)),
AFType::OutputPushPull => block.otyper().modify(|w| w.set_ot(pin, vals::Ot::PUSHPULL)),
AFType::OutputOpenDrain => block.otyper().modify(|w| w.set_ot(pin, vals::Ot::OPENDRAIN)),
}
block.pupdr().modify(|w| w.set_pupdr(pin, pull.into()));
block
.moder()
.modify(|w| w.set_moder(pin, vals::Moder::ALTERNATE));
block.moder().modify(|w| w.set_moder(pin, vals::Moder::ALTERNATE));
}
#[inline]
@ -507,9 +493,7 @@ pub(crate) mod sealed {
});
}
#[cfg(gpio_v2)]
block
.moder()
.modify(|w| w.set_moder(pin, vals::Moder::ANALOG));
block.moder().modify(|w| w.set_moder(pin, vals::Moder::ANALOG));
}
/// Set the pin as "disconnected", ie doing nothing and consuming the lowest
@ -535,9 +519,7 @@ pub(crate) mod sealed {
}
#[cfg(gpio_v2)]
self.block()
.ospeedr()
.modify(|w| w.set_ospeedr(pin, speed.into()));
self.block().ospeedr().modify(|w| w.set_ospeedr(pin, speed.into()));
}
}
}
@ -623,10 +605,9 @@ pub(crate) unsafe fn init() {
}
mod eh02 {
use embedded_hal_02::digital::v2::{InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin};
use super::*;
use embedded_hal_02::digital::v2::{
InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin,
};
impl<'d, T: Pin> InputPin for Input<'d, T> {
type Error = Infallible;
@ -715,12 +696,11 @@ mod eh02 {
#[cfg(feature = "unstable-traits")]
mod eh1 {
use super::*;
use embedded_hal_1::digital::blocking::{
InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin,
};
use embedded_hal_1::digital::blocking::{InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin};
use embedded_hal_1::digital::ErrorType;
use super::*;
impl<'d, T: Pin> ErrorType for Input<'d, T> {
type Error = Infallible;
}

3
embassy-stm32/src/i2c/mod.rs
View File

@ -5,9 +5,10 @@ use crate::interrupt::Interrupt;
#[cfg_attr(i2c_v1, path = "v1.rs")]
#[cfg_attr(i2c_v2, path = "v2.rs")]
mod _version;
use crate::peripherals;
pub use _version::*;
use crate::peripherals;
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {

14
embassy-stm32/src/i2c/v1.rs
View File

@ -1,11 +1,12 @@
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use crate::gpio::sealed::AFType;
use crate::i2c::{Error, Instance, SclPin, SdaPin};
use crate::pac::i2c;
use crate::time::Hertz;
use crate::Unborrow;
pub struct State {}
@ -68,9 +69,7 @@ impl<'d, T: Instance> I2c<'d, T> {
});
}
Self {
phantom: PhantomData,
}
Self { phantom: PhantomData }
}
unsafe fn check_and_clear_error_flags(&self) -> Result<i2c::regs::Sr1, Error> {
@ -249,12 +248,7 @@ impl<'d, T: Instance> I2c<'d, T> {
Ok(())
}
pub fn blocking_write_read(
&mut self,
addr: u8,
bytes: &[u8],
buffer: &mut [u8],
) -> Result<(), Error> {
pub fn blocking_write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
unsafe { self.write_bytes(addr, bytes)? };
self.blocking_read(addr, buffer)?;

100
embassy-stm32/src/i2c/v2.rs
View File

@ -2,8 +2,6 @@ use core::cmp;
use core::marker::PhantomData;
use core::task::Poll;
use crate::interrupt::InterruptExt;
use crate::Unborrow;
use atomic_polyfill::{AtomicUsize, Ordering};
use embassy::waitqueue::AtomicWaker;
use embassy_hal_common::drop::OnDrop;
@ -13,8 +11,10 @@ use futures::future::poll_fn;
use crate::dma::NoDma;
use crate::gpio::sealed::AFType;
use crate::i2c::{Error, Instance, SclPin, SdaPin};
use crate::interrupt::InterruptExt;
use crate::pac::i2c;
use crate::time::Hertz;
use crate::Unborrow;
pub struct State {
waker: AtomicWaker,
@ -277,12 +277,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
}
fn read_internal(
&mut self,
address: u8,
buffer: &mut [u8],
restart: bool,
) -> Result<(), Error> {
fn read_internal(&mut self, address: u8, buffer: &mut [u8], restart: bool) -> Result<(), Error> {
let completed_chunks = buffer.len() / 255;
let total_chunks = if completed_chunks * 255 == buffer.len() {
completed_chunks
@ -335,12 +330,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// ST SAD+W
// NOTE(unsafe) We have &mut self
unsafe {
Self::master_write(
address,
bytes.len().min(255),
Stop::Software,
last_chunk_idx != 0,
);
Self::master_write(address, bytes.len().min(255), Stop::Software, last_chunk_idx != 0);
}
for (number, chunk) in bytes.chunks(255).enumerate() {
@ -467,12 +457,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
Ok(())
}
async fn read_dma_internal(
&mut self,
address: u8,
buffer: &mut [u8],
restart: bool,
) -> Result<(), Error>
async fn read_dma_internal(&mut self, address: u8, buffer: &mut [u8], restart: bool) -> Result<(), Error>
where
RXDMA: crate::i2c::RxDma<T>,
{
@ -513,13 +498,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// NOTE(unsafe) self.rx_dma does not fiddle with the i2c registers
unsafe {
Self::master_read(
address,
total_len.min(255),
Stop::Software,
total_chunks != 1,
restart,
);
Self::master_read(address, total_len.min(255), Stop::Software, total_chunks != 1, restart);
}
poll_fn(|cx| {
@ -597,12 +576,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
}
pub async fn write_read(
&mut self,
address: u8,
bytes: &[u8],
buffer: &mut [u8],
) -> Result<(), Error>
pub async fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error>
where
TXDMA: super::TxDma<T>,
RXDMA: super::RxDma<T>,
@ -634,12 +608,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
self.write_internal(address, bytes, true)
}
pub fn blocking_write_read(
&mut self,
address: u8,
bytes: &[u8],
buffer: &mut [u8],
) -> Result<(), Error> {
pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
self.write_internal(address, bytes, false)?;
self.read_internal(address, buffer, true)
// Automatic Stop
@ -675,10 +644,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
if idx != 0 {
// NOTE(unsafe) We have &mut self
unsafe {
Self::master_continue(
slice_len.min(255),
(idx != last_slice_index) || (slice_len > 255),
);
Self::master_continue(slice_len.min(255), (idx != last_slice_index) || (slice_len > 255));
}
}
@ -686,10 +652,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
if number != 0 {
// NOTE(unsafe) We have &mut self
unsafe {
Self::master_continue(
chunk.len(),
(number != last_chunk_idx) || (idx != last_slice_index),
);
Self::master_continue(chunk.len(), (number != last_chunk_idx) || (idx != last_slice_index));
}
}
@ -737,12 +700,7 @@ mod eh02 {
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
type Error = Error;
fn write_read(
&mut self,
address: u8,
bytes: &[u8],
buffer: &mut [u8],
) -> Result<(), Self::Error> {
fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, bytes, buffer)
}
}
@ -794,10 +752,7 @@ impl Timings {
// For the standard-mode configuration method, we must have a ratio of 4
// or higher
assert!(
ratio >= 4,
"The I2C PCLK must be at least 4 times the bus frequency!"
);
assert!(ratio >= 4, "The I2C PCLK must be at least 4 times the bus frequency!");
let (presc_reg, scll, sclh, sdadel, scldel) = if freq > 100_000 {
// Fast-mode (Fm) or Fast-mode Plus (Fm+)
@ -831,13 +786,7 @@ impl Timings {
(sdadel, scldel)
};
(
presc_reg,
scll as u8,
sclh as u8,
sdadel as u8,
scldel as u8,
)
(presc_reg, scll as u8, sclh as u8, sdadel as u8, scldel as u8)
} else {
// Standard-mode (Sm)
// here we pick SCLL = SCLH
@ -855,21 +804,12 @@ impl Timings {
let scll = sclh;
// Speed check
assert!(
sclh < 256,
"The I2C PCLK is too fast for this bus frequency!"
);
assert!(sclh < 256, "The I2C PCLK is too fast for this bus frequency!");
let sdadel = i2cclk / 2_000_000 / presc;
let scldel = i2cclk / 500_000 / presc - 1;
(
presc_reg,
scll as u8,
sclh as u8,
sdadel as u8,
scldel as u8,
)
(presc_reg, scll as u8, sclh as u8, sdadel as u8, scldel as u8)
};
// Sanity check
@ -900,9 +840,9 @@ mod eh1 {
match *self {
Self::Bus => embedded_hal_1::i2c::ErrorKind::Bus,
Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
Self::Nack => embedded_hal_1::i2c::ErrorKind::NoAcknowledge(
embedded_hal_1::i2c::NoAcknowledgeSource::Unknown,
),
Self::Nack => {
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
}
Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
@ -911,9 +851,7 @@ mod eh1 {
}
}
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_1::i2c::ErrorType
for I2c<'d, T, TXDMA, RXDMA>
{
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_1::i2c::ErrorType for I2c<'d, T, TXDMA, RXDMA> {
type Error = Error;
}
}

14
embassy-stm32/src/lib.rs
View File

@ -1,8 +1,5 @@
#![no_std]
#![cfg_attr(
feature = "nightly",
feature(generic_associated_types, type_alias_impl_trait)
)]
#![cfg_attr(feature = "nightly", feature(generic_associated_types, type_alias_impl_trait))]
// This must go FIRST so that all the other modules see its macros.
pub mod fmt;
@ -42,9 +39,7 @@ pub mod i2c;
#[cfg(crc)]
pub mod crc;
#[cfg(any(
flash_l0, flash_l1, flash_wl, flash_wb, flash_l4, flash_f3, flash_f7, flash_h7
))]
#[cfg(any(flash_l0, flash_l1, flash_wl, flash_wb, flash_l4, flash_f3, flash_f7, flash_h7))]
pub mod flash;
pub mod pwm;
#[cfg(rng)]
@ -77,7 +72,6 @@ pub use _generated::{peripherals, Peripherals};
pub use embassy_cortex_m::executor;
pub use embassy_hal_common::{unborrow, Unborrow};
pub use embassy_macros::cortex_m_interrupt as interrupt;
#[cfg(feature = "unstable-pac")]
pub use stm32_metapac as pac;
#[cfg(not(feature = "unstable-pac"))]
@ -114,8 +108,8 @@ pub fn init(config: Config) -> Peripherals {
cr.set_dbg_standby(true);
}
#[cfg(any(
dbgmcu_f1, dbgmcu_f2, dbgmcu_f3, dbgmcu_f4, dbgmcu_f7, dbgmcu_g4, dbgmcu_f7,
dbgmcu_l0, dbgmcu_l1, dbgmcu_l4, dbgmcu_wb, dbgmcu_wl
dbgmcu_f1, dbgmcu_f2, dbgmcu_f3, dbgmcu_f4, dbgmcu_f7, dbgmcu_g4, dbgmcu_f7, dbgmcu_l0, dbgmcu_l1,
dbgmcu_l4, dbgmcu_wb, dbgmcu_wl
))]
{
cr.set_dbg_sleep(true);

19
embassy-stm32/src/pwm/mod.rs
View File

@ -64,9 +64,7 @@ pub(crate) mod sealed {
unsafe fn get_max_compare_value(&self) -> u16;
}
pub trait CaptureCompare32bitInstance:
crate::timer::sealed::GeneralPurpose32bitInstance
{
pub trait CaptureCompare32bitInstance: crate::timer::sealed::GeneralPurpose32bitInstance {
unsafe fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode);
unsafe fn enable_channel(&mut self, channel: Channel, enable: bool);
@ -82,10 +80,7 @@ pub trait CaptureCompare16bitInstance:
{
}
pub trait CaptureCompare32bitInstance:
sealed::CaptureCompare32bitInstance
+ CaptureCompare16bitInstance
+ crate::timer::GeneralPurpose32bitInstance
+ 'static
sealed::CaptureCompare32bitInstance + CaptureCompare16bitInstance + crate::timer::GeneralPurpose32bitInstance + 'static
{
}
@ -93,11 +88,7 @@ pub trait CaptureCompare32bitInstance:
macro_rules! impl_compare_capable_16bit {
($inst:ident) => {
impl crate::pwm::sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {
unsafe fn set_output_compare_mode(
&mut self,
channel: crate::pwm::Channel,
mode: OutputCompareMode,
) {
unsafe fn set_output_compare_mode(&mut self, channel: crate::pwm::Channel, mode: OutputCompareMode) {
use crate::timer::sealed::GeneralPurpose16bitInstance;
let r = Self::regs_gp16();
let raw_channel: usize = channel.raw();
@ -114,9 +105,7 @@ macro_rules! impl_compare_capable_16bit {
unsafe fn set_compare_value(&mut self, channel: Channel, value: u16) {
use crate::timer::sealed::GeneralPurpose16bitInstance;
Self::regs_gp16()
.ccr(channel.raw())
.modify(|w| w.set_ccr(value));
Self::regs_gp16().ccr(channel.raw()).modify(|w| w.set_ccr(value));
}
unsafe fn get_max_compare_value(&self) -> u16 {

9
embassy-stm32/src/pwm/simple_pwm.rs
View File

@ -1,11 +1,12 @@
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use super::*;
#[allow(unused_imports)]
use crate::gpio::sealed::{AFType, Pin};
use crate::time::Hertz;
use crate::Unborrow;
pub struct SimplePwm<'d, T> {
phantom: PhantomData<&'d mut T>,
@ -74,11 +75,7 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
})
}
fn new_inner<F: Into<Hertz>>(
tim: impl Unborrow<Target = T> + 'd,
freq: F,
configure_pins: impl FnOnce(),
) -> Self {
fn new_inner<F: Into<Hertz>>(tim: impl Unborrow<Target = T> + 'd, freq: F, configure_pins: impl FnOnce()) -> Self {
unborrow!(tim);
T::enable();

6
embassy-stm32/src/rcc/f0.rs
View File

@ -1,9 +1,8 @@
use super::{set_freqs, Clocks};
use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
use super::{set_freqs, Clocks};
const HSI: u32 = 8_000_000;
/// Configuration of the clocks
@ -112,8 +111,7 @@ pub(crate) unsafe fn init(config: Config) {
while !RCC.cr2().read().hsi48rdy() {}
if pllmul_bits.is_some() {
RCC.cfgr()
.modify(|w| w.set_pllsrc(Pllsrc::HSI48_DIV_PREDIV))
RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI48_DIV_PREDIV))
}
}
_ => {

4
embassy-stm32/src/rcc/f2.rs
View File

@ -436,9 +436,7 @@ pub(crate) unsafe fn init(config: Config) {
let pll_clocks = config.pll.clocks(pll_src_freq);
assert!(Hertz(950_000) <= pll_clocks.in_freq && pll_clocks.in_freq <= Hertz(2_100_000));
assert!(Hertz(192_000_000) <= pll_clocks.vco_freq && pll_clocks.vco_freq <= Hertz(432_000_000));
assert!(
Hertz(24_000_000) <= pll_clocks.main_freq && pll_clocks.main_freq <= Hertz(120_000_000)
);
assert!(Hertz(24_000_000) <= pll_clocks.main_freq && pll_clocks.main_freq <= Hertz(120_000_000));
// USB actually requires == 48 MHz, but other PLL48 peripherals are fine with <= 48MHz
assert!(pll_clocks.pll48_freq <= Hertz(48_000_000));

26
embassy-stm32/src/rcc/f4.rs
View File

@ -20,18 +20,12 @@ pub struct Config {
pub pll48: bool,
}
unsafe fn setup_pll(
pllsrcclk: u32,
use_hse: bool,
pllsysclk: Option<u32>,
pll48clk: bool,
) -> PllResults {
unsafe fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
use crate::pac::rcc::vals::{Pllp, Pllsrc};
let sysclk = pllsysclk.unwrap_or(pllsrcclk);
if pllsysclk.is_none() && !pll48clk {
RCC.pllcfgr()
.modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
return PllResults {
use_pll: false,
@ -47,11 +41,7 @@ unsafe fn setup_pll(
// Sysclk output divisor must be one of 2, 4, 6 or 8
let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
let target_freq = if pll48clk {
48_000_000
} else {
sysclk * sysclk_div
};
let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
// Find the lowest pllm value that minimize the difference between
// target frequency and the real vco_out frequency.
@ -135,11 +125,7 @@ pub(crate) unsafe fn init(config: Config) {
assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
}
let sysclk = if sysclk_on_pll {
unwrap!(plls.pllsysclk)
} else {
sysclk
};
let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
// AHB prescaler
let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
@ -269,9 +255,7 @@ mod max {
pub(crate) const SYSCLK_MAX: u32 = 168_000_000;
#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
pub(crate) const SYSCLK_MAX: u32 = 100_000_000;
#[cfg(any(
stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,
))]
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
pub(crate) const SYSCLK_MAX: u32 = 180_000_000;
pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 168_000_000;

22
embassy-stm32/src/rcc/f7.rs
View File

@ -21,18 +21,12 @@ pub struct Config {
pub pll48: bool,
}
unsafe fn setup_pll(
pllsrcclk: u32,
use_hse: bool,
pllsysclk: Option<u32>,
pll48clk: bool,
) -> PllResults {
unsafe fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
use crate::pac::rcc::vals::{Pllp, Pllsrc};
let sysclk = pllsysclk.unwrap_or(pllsrcclk);
if pllsysclk.is_none() && !pll48clk {
RCC.pllcfgr()
.modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
return PllResults {
use_pll: false,
@ -48,11 +42,7 @@ unsafe fn setup_pll(
// Sysclk output divisor must be one of 2, 4, 6 or 8
let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
let target_freq = if pll48clk {
48_000_000
} else {
sysclk * sysclk_div
};
let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
// Find the lowest pllm value that minimize the difference between
// target frequency and the real vco_out frequency.
@ -146,11 +136,7 @@ pub(crate) unsafe fn init(config: Config) {
assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
}
let sysclk = if sysclk_on_pll {
unwrap!(plls.pllsysclk)
} else {
sysclk
};
let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
// AHB prescaler
let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);

3
embassy-stm32/src/rcc/g0.rs
View File

@ -2,8 +2,7 @@ use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::{self, Hpre, Hsidiv, Ppre, Sw};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::time::U32Ext;
use crate::time::{Hertz, U32Ext};
/// HSI speed
pub const HSI_FREQ: u32 = 16_000_000;

3
embassy-stm32/src/rcc/g4.rs
View File

@ -1,7 +1,6 @@
use crate::pac::{PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::time::U32Ext;
use crate::time::{Hertz, U32Ext};
/// HSI speed
pub const HSI_FREQ: u32 = 16_000_000;

60
embassy-stm32/src/rcc/h7.rs
View File

@ -1,19 +1,16 @@
use core::marker::PhantomData;
use crate::Unborrow;
use embassy_hal_common::unborrow;
pub use pll::PllConfig;
use stm32_metapac::rcc::vals::{Mco1, Mco2};
use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
use crate::pac::rcc::vals::Timpre;
use crate::pac::rcc::vals::{Adcsel, Ckpersel, Dppre, Hpre, Hsidiv, Pllsrc, Sw};
use crate::pac::rcc::vals::{Adcsel, Ckpersel, Dppre, Hpre, Hsidiv, Pllsrc, Sw, Timpre};
use crate::pac::{PWR, RCC, SYSCFG};
use crate::peripherals;
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
pub use pll::PllConfig;
use crate::{peripherals, Unborrow};
const HSI: Hertz = Hertz(64_000_000);
const CSI: Hertz = Hertz(4_000_000);
@ -181,8 +178,10 @@ fn sys_ck_setup(config: &mut Config, srcclk: Hertz) -> (Hertz, bool) {
// Therefore we must use pll1_p_ck
let pll1_p_ck = match config.pll1.p_ck {
Some(p_ck) => {
assert!(p_ck == sys_ck,
"Error: Cannot set pll1_p_ck independently as it must be used to generate sys_ck");
assert!(
p_ck == sys_ck,
"Error: Cannot set pll1_p_ck independently as it must be used to generate sys_ck"
);
Some(p_ck)
}
None => Some(sys_ck),
@ -392,9 +391,7 @@ impl<'d, T: McoInstance> Mco<'d, T> {
pin.set_speed(Speed::VeryHigh);
});
Self {
phantom: PhantomData,
}
Self { phantom: PhantomData }
}
}
@ -538,33 +535,19 @@ pub(crate) unsafe fn init(mut config: Config) {
// Timer prescaler selection
let timpre = Timpre::DEFAULTX2;
let requested_pclk1 = config
.pclk1
.map(|v| v.0)
.unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
let requested_pclk1 = config.pclk1.map(|v| v.0).unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
let (rcc_pclk1, ppre1_bits, ppre1, rcc_timerx_ker_ck) =
ppre_calculate(requested_pclk1, rcc_hclk, pclk_max, Some(timpre));
let requested_pclk2 = config
.pclk2
.map(|v| v.0)
.unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
let requested_pclk2 = config.pclk2.map(|v| v.0).unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
let (rcc_pclk2, ppre2_bits, ppre2, rcc_timery_ker_ck) =
ppre_calculate(requested_pclk2, rcc_hclk, pclk_max, Some(timpre));
let requested_pclk3 = config
.pclk3
.map(|v| v.0)
.unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
let (rcc_pclk3, ppre3_bits, ppre3, _) =
ppre_calculate(requested_pclk3, rcc_hclk, pclk_max, None);
let requested_pclk3 = config.pclk3.map(|v| v.0).unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
let (rcc_pclk3, ppre3_bits, ppre3, _) = ppre_calculate(requested_pclk3, rcc_hclk, pclk_max, None);
let requested_pclk4 = config
.pclk4
.map(|v| v.0)
.unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
let (rcc_pclk4, ppre4_bits, ppre4, _) =
ppre_calculate(requested_pclk4, rcc_hclk, pclk_max, None);
let requested_pclk4 = config.pclk4.map(|v| v.0).unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
let (rcc_pclk4, ppre4_bits, ppre4, _) = ppre_calculate(requested_pclk4, rcc_hclk, pclk_max, None);
flash_setup(rcc_aclk, pwr_vos);
@ -593,11 +576,7 @@ pub(crate) unsafe fn init(mut config: Config) {
None => None,
};
let pllsrc = if config.hse.is_some() {
Pllsrc::HSE
} else {
Pllsrc::HSI
};
let pllsrc = if config.hse.is_some() { Pllsrc::HSE } else { Pllsrc::HSI };
RCC.pllckselr().modify(|w| w.set_pllsrc(pllsrc));
let enable_pll = |pll| {
@ -640,8 +619,7 @@ pub(crate) unsafe fn init(mut config: Config) {
RCC.d1ccipr().modify(|w| w.set_ckpersel(ckpersel));
// ADC clock MUX
RCC.d3ccipr()
.modify(|w| w.set_adcsel(config.adc_clock_source.adcsel()));
RCC.d3ccipr().modify(|w| w.set_adcsel(config.adc_clock_source.adcsel()));
let adc_ker_ck = match config.adc_clock_source {
AdcClockSource::Pll2PCk => pll2_p_ck.map(Hertz),
@ -823,15 +801,13 @@ mod pll {
let pll_x_n = vco_ck_target / ref_x_ck;
assert!(pll_x_n >= 4);
assert!(pll_x_n <= 512);
RCC.plldivr(plln)
.modify(|w| w.set_divn1((pll_x_n - 1) as u16));
RCC.plldivr(plln).modify(|w| w.set_divn1((pll_x_n - 1) as u16));
// No FRACN
RCC.pllcfgr().modify(|w| w.set_pllfracen(plln, false));
let vco_ck = ref_x_ck * pll_x_n;
RCC.plldivr(plln)
.modify(|w| w.set_divp1(Divp((pll_x_p - 1) as u8)));
RCC.plldivr(plln).modify(|w| w.set_divp1(Divp((pll_x_p - 1) as u8)));
RCC.pllcfgr().modify(|w| w.set_divpen(plln, true));
// Calulate additional output dividers

3
embassy-stm32/src/rcc/l0.rs
View File

@ -3,8 +3,7 @@ use crate::pac::RCC;
#[cfg(crs)]
use crate::pac::{CRS, SYSCFG};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::time::U32Ext;
use crate::time::{Hertz, U32Ext};
/// HSI16 speed
pub const HSI16_FREQ: u32 = 16_000_000;

3
embassy-stm32/src/rcc/l1.rs
View File

@ -1,8 +1,7 @@
use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::time::U32Ext;
use crate::time::{Hertz, U32Ext};
/// HSI speed
pub const HSI_FREQ: u32 = 16_000_000;

3
embassy-stm32/src/rcc/l4.rs
View File

@ -1,8 +1,7 @@
use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::time::U32Ext;
use crate::time::{Hertz, U32Ext};
/// HSI16 speed
pub const HSI16_FREQ: u32 = 16_000_000;

6
embassy-stm32/src/rcc/l5.rs
View File

@ -3,8 +3,7 @@ use stm32_metapac::PWR;
use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::time::U32Ext;
use crate::time::{Hertz, U32Ext};
/// HSI16 speed
pub const HSI16_FREQ: u32 = 16_000_000;
@ -297,8 +296,7 @@ impl Default for Config {
}
pub(crate) unsafe fn init(config: Config) {
PWR.cr1()
.modify(|w| w.set_vos(stm32_metapac::pwr::vals::Vos::RANGE0));
PWR.cr1().modify(|w| w.set_vos(stm32_metapac::pwr::vals::Vos::RANGE0));
let (sys_clk, sw) = match config.mux {
ClockSrc::MSI(range) => {
// Enable MSI

9
embassy-stm32/src/rcc/mod.rs
View File

@ -1,8 +1,9 @@
#![macro_use]
use crate::time::Hertz;
use core::mem::MaybeUninit;
use crate::time::Hertz;
#[cfg_attr(rcc_f0, path = "f0.rs")]
#[cfg_attr(any(rcc_f1, rcc_f1cl), path = "f1.rs")]
#[cfg_attr(rcc_f2, path = "f2.rs")]
@ -41,13 +42,11 @@ pub struct Clocks {
// AHB
pub ahb1: Hertz,
#[cfg(any(
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb,
rcc_wl5, rcc_wle
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb, rcc_wl5, rcc_wle
))]
pub ahb2: Hertz,
#[cfg(any(
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb,
rcc_wl5, rcc_wle
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5, rcc_wle
))]
pub ahb3: Hertz,
#[cfg(any(rcc_h7, rcc_h7ab))]

3
embassy-stm32/src/rcc/u5.rs
View File

@ -1,7 +1,8 @@
use stm32_metapac::rcc::vals::{Hpre, Msirange, Msirgsel, Pllm, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::{Hertz, U32Ext};
use stm32_metapac::rcc::vals::{Hpre, Msirange, Msirgsel, Pllm, Pllsrc, Ppre, Sw};
/// HSI16 speed
pub const HSI16_FREQ: u32 = 16_000_000;

3
embassy-stm32/src/rcc/wb.rs
View File

@ -1,7 +1,6 @@
use crate::pac::RCC;
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::time::U32Ext;
use crate::time::{Hertz, U32Ext};
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
/// and with the addition of the init function to configure a system clock.

5
embassy-stm32/src/rng.rs
View File

@ -1,15 +1,14 @@
#![macro_use]
use crate::Unborrow;
use core::marker::PhantomData;
use core::task::Poll;
use embassy::waitqueue::AtomicWaker;
use embassy_hal_common::unborrow;
use futures::future::poll_fn;
use rand_core::{CryptoRng, RngCore};
use crate::pac;
use crate::peripherals;
use crate::{pac, peripherals, Unborrow};
pub(crate) static RNG_WAKER: AtomicWaker = AtomicWaker::new();

91
embassy-stm32/src/sdmmc/mod.rs
View File

@ -4,8 +4,6 @@ use core::default::Default;
use core::marker::PhantomData;
use core::task::Poll;
use crate::interrupt::InterruptExt;
use crate::Unborrow;
use embassy::waitqueue::AtomicWaker;
use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::unborrow;
@ -15,11 +13,11 @@ use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID,
use crate::dma::NoDma;
use crate::gpio::sealed::AFType;
use crate::gpio::{Pull, Speed};
use crate::interrupt::Interrupt;
use crate::interrupt::{Interrupt, InterruptExt};
use crate::pac::sdmmc::Sdmmc as RegBlock;
use crate::peripherals;
use crate::rcc::RccPeripheral;
use crate::time::Hertz;
use crate::{peripherals, Unborrow};
/// The signalling scheme used on the SDMMC bus
#[non_exhaustive]
@ -283,11 +281,7 @@ impl<'d, T: Instance, P: Pins<T>, Dma: SdmmcDma<T>> Sdmmc<'d, T, P, Dma> {
}
#[inline(always)]
pub async fn read_block(
&mut self,
block_idx: u32,
buffer: &mut DataBlock,
) -> Result<(), Error> {
pub async fn read_block(&mut self, block_idx: u32, buffer: &mut DataBlock) -> Result<(), Error> {
let card_capacity = self.card()?.card_type;
let inner = T::inner();
let state = T::state();
@ -475,8 +469,7 @@ impl SdmmcInner {
self.select_card(Some(&card))?;
self.get_scr(&mut card, waker_reg, data_transfer_timeout, dma)
.await?;
self.get_scr(&mut card, waker_reg, data_transfer_timeout, dma).await?;
// Set bus width
let (width, acmd_arg) = match bus_width {
@ -515,12 +508,7 @@ impl SdmmcInner {
if freq.0 > 25_000_000 {
// Switch to SDR25
*signalling = self
.switch_signalling_mode(
Signalling::SDR25,
waker_reg,
data_transfer_timeout,
dma,
)
.switch_signalling_mode(Signalling::SDR25, waker_reg, data_transfer_timeout, dma)
.await?;
if *signalling == Signalling::SDR25 {
@ -562,13 +550,7 @@ impl SdmmcInner {
let on_drop = OnDrop::new(|| unsafe { self.on_drop() });
unsafe {
self.prepare_datapath_read(
buffer as *mut [u32; 128],
512,
9,
data_transfer_timeout,
dma,
);
self.prepare_datapath_read(buffer as *mut [u32; 128], 512, 9, data_transfer_timeout, dma);
self.data_interrupts(true);
}
self.cmd(Cmd::read_single_block(address), true)?;
@ -617,13 +599,7 @@ impl SdmmcInner {
let on_drop = OnDrop::new(|| unsafe { self.on_drop() });
unsafe {
self.prepare_datapath_write(
buffer as *const [u32; 128],
512,
9,
data_transfer_timeout,
dma,
);
self.prepare_datapath_write(buffer as *const [u32; 128], 512, 9, data_transfer_timeout, dma);
self.data_interrupts(true);
}
self.cmd(Cmd::write_single_block(address), true)?;
@ -654,10 +630,7 @@ impl SdmmcInner {
// Try to read card status (ACMD13)
while timeout > 0 {
match self
.read_sd_status(card, waker_reg, data_transfer_timeout, dma)
.await
{
match self.read_sd_status(card, waker_reg, data_transfer_timeout, dma).await {
Ok(_) => return Ok(()),
Err(Error::Timeout) => (), // Try again
Err(e) => return Err(e),
@ -732,8 +705,7 @@ impl SdmmcInner {
// NOTE(unsafe) We have exclusive access to the regisers
regs.dtimer()
.write(|w| w.set_datatime(data_transfer_timeout));
regs.dtimer().write(|w| w.set_datatime(data_transfer_timeout));
regs.dlenr().write(|w| w.set_datalength(length_bytes));
cfg_if::cfg_if! {
@ -781,8 +753,7 @@ impl SdmmcInner {
// NOTE(unsafe) We have exclusive access to the regisers
regs.dtimer()
.write(|w| w.set_datatime(data_transfer_timeout));
regs.dtimer().write(|w| w.set_datatime(data_transfer_timeout));
regs.dlenr().write(|w| w.set_datalength(length_bytes));
cfg_if::cfg_if! {
@ -824,13 +795,7 @@ impl SdmmcInner {
}
/// Sets the CLKDIV field in CLKCR. Updates clock field in self
fn clkcr_set_clkdiv(
&self,
freq: u32,
width: BusWidth,
ker_ck: Hertz,
clock: &mut Hertz,
) -> Result<(), Error> {
fn clkcr_set_clkdiv(&self, freq: u32, width: BusWidth, ker_ck: Hertz, clock: &mut Hertz) -> Result<(), Error> {
let regs = self.0;
let (clkdiv, new_clock) = clk_div(ker_ck, freq)?;
@ -882,13 +847,7 @@ impl SdmmcInner {
let on_drop = OnDrop::new(|| unsafe { self.on_drop() });
unsafe {
self.prepare_datapath_read(
&mut status as *mut [u32; 16],
64,
6,
data_transfer_timeout,
dma,
);
self.prepare_datapath_read(&mut status as *mut [u32; 16], 64, 6, data_transfer_timeout, dma);
self.data_interrupts(true);
}
self.cmd(Cmd::cmd6(set_function), true)?; // CMD6
@ -970,13 +929,7 @@ impl SdmmcInner {
let on_drop = OnDrop::new(|| unsafe { self.on_drop() });
unsafe {
self.prepare_datapath_read(
&mut status as *mut [u32; 16],
64,
6,
data_transfer_timeout,
dma,
);
self.prepare_datapath_read(&mut status as *mut [u32; 16], 64, 6, data_transfer_timeout, dma);
self.data_interrupts(true);
}
self.cmd(Cmd::card_status(0), true)?;
@ -1473,10 +1426,12 @@ foreach_peripheral!(
#[cfg(feature = "sdmmc-rs")]
mod sdmmc_rs {
use super::*;
use core::future::Future;
use embedded_sdmmc::{Block, BlockCount, BlockDevice, BlockIdx};
use super::*;
impl<'d, T: Instance, P: Pins<T>> BlockDevice for Sdmmc<'d, T, P> {
type Error = Error;
type ReadFuture<'a>
@ -1506,13 +1461,7 @@ mod sdmmc_rs {
// NOTE(unsafe) Block uses align(4)
let buf = unsafe { &mut *(block as *mut [u8; 512] as *mut [u32; 128]) };
inner
.read_block(
address,
buf,
card_capacity,
state,
self.config.data_transfer_timeout,
)
.read_block(address, buf, card_capacity, state, self.config.data_transfer_timeout)
.await?;
address += 1;
}
@ -1520,11 +1469,7 @@ mod sdmmc_rs {
}
}
fn write<'a>(
&'a mut self,
blocks: &'a [Block],
start_block_idx: BlockIdx,
) -> Self::WriteFuture<'a> {
fn write<'a>(&'a mut self, blocks: &'a [Block], start_block_idx: BlockIdx) -> Self::WriteFuture<'a> {
async move {
let card = self.card.as_mut().ok_or(Error::NoCard)?;
let inner = T::inner();

64
embassy-stm32/src/spi/mod.rs
View File

@ -1,22 +1,20 @@
#![macro_use]
use crate::Unborrow;
use core::marker::PhantomData;
use core::ptr;
use embassy_hal_common::unborrow;
pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::join;
use self::sealed::WordSize;
use crate::dma::{slice_ptr_parts, NoDma, Transfer};
use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::AnyPin;
use crate::pac::spi::Spi as Regs;
use crate::pac::spi::{regs, vals};
use crate::peripherals;
use crate::pac::spi::{regs, vals, Spi as Regs};
use crate::rcc::RccPeripheral;
use crate::time::Hertz;
pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use crate::{peripherals, Unborrow};
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@ -423,10 +421,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let tx_request = self.txdma.request();
let tx_dst = T::REGS.tx_ptr();
unsafe {
self.txdma
.start_write(tx_request, data, tx_dst, Default::default())
}
unsafe { self.txdma.start_write(tx_request, data, tx_dst, Default::default()) }
let tx_f = Transfer::new(&mut self.txdma);
unsafe {
@ -472,22 +467,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::REGS.rx_ptr();
unsafe {
self.rxdma
.start_read(rx_request, rx_src, data, Default::default())
};
unsafe { self.rxdma.start_read(rx_request, rx_src, data, Default::default()) };
let rx_f = Transfer::new(&mut self.rxdma);
let tx_request = self.txdma.request();
let tx_dst = T::REGS.tx_ptr();
let clock_byte = 0x00u8;
let tx_f = crate::dma::write_repeated(
&mut self.txdma,
tx_request,
clock_byte,
clock_byte_count,
tx_dst,
);
let tx_f = crate::dma::write_repeated(&mut self.txdma, tx_request, clock_byte, clock_byte_count, tx_dst);
unsafe {
set_txdmaen(T::REGS, true);
@ -507,11 +493,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Ok(())
}
async fn transfer_inner<W: Word>(
&mut self,
read: *mut [W],
write: *const [W],
) -> Result<(), Error>
async fn transfer_inner<W: Word>(&mut self, read: *mut [W], write: *const [W]) -> Result<(), Error>
where
Tx: TxDma<T>,
Rx: RxDma<T>,
@ -537,18 +519,12 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::REGS.rx_ptr();
unsafe {
self.rxdma
.start_read(rx_request, rx_src, read, Default::default())
};
unsafe { self.rxdma.start_read(rx_request, rx_src, read, Default::default()) };
let rx_f = Transfer::new(&mut self.rxdma);
let tx_request = self.txdma.request();
let tx_dst = T::REGS.tx_ptr();
unsafe {
self.txdma
.start_write(tx_request, write, tx_dst, Default::default())
}
unsafe { self.txdma.start_write(tx_request, write, tx_dst, Default::default()) }
let tx_f = Transfer::new(&mut self.txdma);
unsafe {
@ -835,9 +811,7 @@ mod eh02 {
// some marker traits. For details, see https://github.com/rust-embedded/embedded-hal/pull/289
macro_rules! impl_blocking {
($w:ident) => {
impl<'d, T: Instance> embedded_hal_02::blocking::spi::Write<$w>
for Spi<'d, T, NoDma, NoDma>
{
impl<'d, T: Instance> embedded_hal_02::blocking::spi::Write<$w> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn write(&mut self, words: &[$w]) -> Result<(), Self::Error> {
@ -845,9 +819,7 @@ mod eh02 {
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::spi::Transfer<$w>
for Spi<'d, T, NoDma, NoDma>
{
impl<'d, T: Instance> embedded_hal_02::blocking::spi::Transfer<$w> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [$w]) -> Result<&'w [$w], Self::Error> {
@ -876,25 +848,19 @@ mod eh1 {
}
}
impl<'d, T: Instance, W: Word> embedded_hal_1::spi::blocking::SpiBusRead<W>
for Spi<'d, T, NoDma, NoDma>
{
impl<'d, T: Instance, W: Word> embedded_hal_1::spi::blocking::SpiBusRead<W> for Spi<'d, T, NoDma, NoDma> {
fn read(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.blocking_read(words)
}
}
impl<'d, T: Instance, W: Word> embedded_hal_1::spi::blocking::SpiBusWrite<W>
for Spi<'d, T, NoDma, NoDma>
{
impl<'d, T: Instance, W: Word> embedded_hal_1::spi::blocking::SpiBusWrite<W> for Spi<'d, T, NoDma, NoDma> {
fn write(&mut self, words: &[W]) -> Result<(), Self::Error> {
self.blocking_write(words)
}
}
impl<'d, T: Instance, W: Word> embedded_hal_1::spi::blocking::SpiBus<W>
for Spi<'d, T, NoDma, NoDma>
{
impl<'d, T: Instance, W: Word> embedded_hal_1::spi::blocking::SpiBus<W> for Spi<'d, T, NoDma, NoDma> {
fn transfer(&mut self, read: &mut [W], write: &[W]) -> Result<(), Self::Error> {
self.blocking_transfer(read, write)
}

55
embassy-stm32/src/subghz/mod.rs
View File

@ -43,19 +43,20 @@ mod value_error;
pub use bit_sync::BitSync;
pub use cad_params::{CadParams, ExitMode, NbCadSymbol};
pub use calibrate::{Calibrate, CalibrateImage};
use embassy_hal_common::ratio::Ratio;
pub use fallback_mode::FallbackMode;
pub use hse_trim::HseTrim;
pub use irq::{CfgIrq, Irq, IrqLine};
pub use lora_sync_word::LoRaSyncWord;
pub use mod_params::BpskModParams;
pub use mod_params::{CodingRate, LoRaBandwidth, LoRaModParams, SpreadingFactor};
pub use mod_params::{FskBandwidth, FskBitrate, FskFdev, FskModParams, FskPulseShape};
pub use mod_params::{
BpskModParams, CodingRate, FskBandwidth, FskBitrate, FskFdev, FskModParams, FskPulseShape, LoRaBandwidth,
LoRaModParams, SpreadingFactor,
};
pub use ocp::Ocp;
pub use op_error::OpError;
pub use pa_config::{PaConfig, PaSel};
pub use packet_params::{
AddrComp, BpskPacketParams, CrcType, GenericPacketParams, HeaderType, LoRaPacketParams,
PreambleDetection,
AddrComp, BpskPacketParams, CrcType, GenericPacketParams, HeaderType, LoRaPacketParams, PreambleDetection,
};
pub use packet_status::{FskPacketStatus, LoRaPacketStatus};
pub use packet_type::PacketType;
@ -75,17 +76,12 @@ pub use timeout::Timeout;
pub use tx_params::{RampTime, TxParams};
pub use value_error::ValueError;
use embassy_hal_common::ratio::Ratio;
use crate::Unborrow;
use crate::{
dma::NoDma,
pac,
peripherals::SUBGHZSPI,
rcc::sealed::RccPeripheral,
spi::{BitOrder, Config as SpiConfig, MisoPin, MosiPin, SckPin, Spi, MODE_0},
time::Hertz,
};
use crate::dma::NoDma;
use crate::peripherals::SUBGHZSPI;
use crate::rcc::sealed::RccPeripheral;
use crate::spi::{BitOrder, Config as SpiConfig, MisoPin, MosiPin, SckPin, Spi, MODE_0};
use crate::time::Hertz;
use crate::{pac, Unborrow};
/// Passthrough for SPI errors (for now)
pub type Error = crate::spi::Error;
@ -105,8 +101,7 @@ impl Nss {
fn clear() {
let pwr = pac::PWR;
unsafe {
pwr.subghzspicr()
.modify(|w| w.set_nss(pac::pwr::vals::Nss::LOW));
pwr.subghzspicr().modify(|w| w.set_nss(pac::pwr::vals::Nss::LOW));
}
}
@ -115,8 +110,7 @@ impl Nss {
fn set() {
let pwr = pac::PWR;
unsafe {
pwr.subghzspicr()
.modify(|w| w.set_nss(pac::pwr::vals::Nss::HIGH));
pwr.subghzspicr().modify(|w| w.set_nss(pac::pwr::vals::Nss::HIGH));
}
}
}
@ -286,8 +280,7 @@ impl<'d> SubGhz<'d, NoDma, NoDma> {
self.poll_not_busy();
{
let _nss: Nss = Nss::new();
self.spi
.blocking_write(&[OpCode::WriteBuffer as u8, offset])?;
self.spi.blocking_write(&[OpCode::WriteBuffer as u8, offset])?;
self.spi.blocking_write(data)?;
}
self.poll_not_busy();
@ -305,8 +298,7 @@ impl<'d> SubGhz<'d, NoDma, NoDma> {
self.poll_not_busy();
{
let _nss: Nss = Nss::new();
self.spi
.blocking_write(&[OpCode::ReadBuffer as u8, offset])?;
self.spi.blocking_write(&[OpCode::ReadBuffer as u8, offset])?;
self.spi.blocking_transfer_in_place(&mut status_buf)?;
self.spi.blocking_transfer_in_place(buf)?;
}
@ -678,10 +670,7 @@ impl<'d> SubGhz<'d, NoDma, NoDma> {
/// # Ok::<(), embassy_stm32::subghz::Error>(())
/// ```
pub fn set_rx_timeout_stop(&mut self, rx_timeout_stop: RxTimeoutStop) -> Result<(), Error> {
self.write(&[
OpCode::SetStopRxTimerOnPreamble.into(),
rx_timeout_stop.into(),
])
self.write(&[OpCode::SetStopRxTimerOnPreamble.into(), rx_timeout_stop.into()])
}
/// Put the radio in non-continuous RX mode.
@ -730,11 +719,7 @@ impl<'d> SubGhz<'d, NoDma, NoDma> {
/// [`RxDone`]: crate::subghz::Irq::RxDone
/// [`set_rf_frequency`]: crate::subghz::SubGhz::set_rf_frequency
/// [`set_standby`]: crate::subghz::SubGhz::set_standby
pub fn set_rx_duty_cycle(
&mut self,
rx_period: Timeout,
sleep_period: Timeout,
) -> Result<(), Error> {
pub fn set_rx_duty_cycle(&mut self, rx_period: Timeout, sleep_period: Timeout) -> Result<(), Error> {
let rx_period_bits: u32 = rx_period.into_bits();
let sleep_period_bits: u32 = sleep_period.into_bits();
self.write(&[
@ -1288,9 +1273,7 @@ impl<'d> SubGhz<'d, NoDma, NoDma> {
/// # Ok::<(), embassy_stm32::subghz::Error>(())
/// ```
pub fn lora_packet_status(&mut self) -> Result<LoRaPacketStatus, Error> {
Ok(LoRaPacketStatus::from(
self.read_n(OpCode::GetPacketStatus)?,
))
Ok(LoRaPacketStatus::from(self.read_n(OpCode::GetPacketStatus)?))
}
/// Get the instantaneous signal strength during packet reception.

35
embassy-stm32/src/subghz/pa_config.rs
View File

@ -13,58 +13,37 @@ impl PaConfig {
/// Optimal settings for +15dBm output power with the low-power PA.
///
/// This must be used with [`TxParams::LP_15`](super::TxParams::LP_15).
pub const LP_15: PaConfig = PaConfig::new()
.set_pa_duty_cycle(0x6)
.set_hp_max(0x0)
.set_pa(PaSel::Lp);
pub const LP_15: PaConfig = PaConfig::new().set_pa_duty_cycle(0x6).set_hp_max(0x0).set_pa(PaSel::Lp);
/// Optimal settings for +14dBm output power with the low-power PA.
///
/// This must be used with [`TxParams::LP_14`](super::TxParams::LP_14).
pub const LP_14: PaConfig = PaConfig::new()
.set_pa_duty_cycle(0x4)
.set_hp_max(0x0)
.set_pa(PaSel::Lp);
pub const LP_14: PaConfig = PaConfig::new().set_pa_duty_cycle(0x4).set_hp_max(0x0).set_pa(PaSel::Lp);
/// Optimal settings for +10dBm output power with the low-power PA.
///
/// This must be used with [`TxParams::LP_10`](super::TxParams::LP_10).
pub const LP_10: PaConfig = PaConfig::new()
.set_pa_duty_cycle(0x1)
.set_hp_max(0x0)
.set_pa(PaSel::Lp);
pub const LP_10: PaConfig = PaConfig::new().set_pa_duty_cycle(0x1).set_hp_max(0x0).set_pa(PaSel::Lp);
/// Optimal settings for +22dBm output power with the high-power PA.
///
/// This must be used with [`TxParams::HP`](super::TxParams::HP).
pub const HP_22: PaConfig = PaConfig::new()
.set_pa_duty_cycle(0x4)
.set_hp_max(0x7)
.set_pa(PaSel::Hp);
pub const HP_22: PaConfig = PaConfig::new().set_pa_duty_cycle(0x4).set_hp_max(0x7).set_pa(PaSel::Hp);
/// Optimal settings for +20dBm output power with the high-power PA.
///
/// This must be used with [`TxParams::HP`](super::TxParams::HP).
pub const HP_20: PaConfig = PaConfig::new()
.set_pa_duty_cycle(0x3)
.set_hp_max(0x5)
.set_pa(PaSel::Hp);
pub const HP_20: PaConfig = PaConfig::new().set_pa_duty_cycle(0x3).set_hp_max(0x5).set_pa(PaSel::Hp);
/// Optimal settings for +17dBm output power with the high-power PA.
///
/// This must be used with [`TxParams::HP`](super::TxParams::HP).
pub const HP_17: PaConfig = PaConfig::new()
.set_pa_duty_cycle(0x2)
.set_hp_max(0x3)
.set_pa(PaSel::Hp);
pub const HP_17: PaConfig = PaConfig::new().set_pa_duty_cycle(0x2).set_hp_max(0x3).set_pa(PaSel::Hp);
/// Optimal settings for +14dBm output power with the high-power PA.
///
/// This must be used with [`TxParams::HP`](super::TxParams::HP).
pub const HP_14: PaConfig = PaConfig::new()
.set_pa_duty_cycle(0x2)
.set_hp_max(0x2)
.set_pa(PaSel::Hp);
pub const HP_14: PaConfig = PaConfig::new().set_pa_duty_cycle(0x2).set_hp_max(0x2).set_pa(PaSel::Hp);
/// Create a new `PaConfig` struct.
///

5
embassy-stm32/src/subghz/packet_params.rs
View File

@ -147,10 +147,7 @@ impl GenericPacketParams {
/// # assert_eq!(PKT_PARAMS.as_slice()[3], 0x4);
/// ```
#[must_use = "set_preamble_detection returns a modified GenericPacketParams"]
pub const fn set_preamble_detection(
mut self,
pb_det: PreambleDetection,
) -> GenericPacketParams {
pub const fn set_preamble_detection(mut self, pb_det: PreambleDetection) -> GenericPacketParams {
self.buf[3] = pb_det as u8;
self
}

4
embassy-stm32/src/subghz/packet_status.rs
View File

@ -1,6 +1,4 @@
use super::Ratio;
use super::Status;
use super::{Ratio, Status};
/// (G)FSK packet status.
///

5
embassy-stm32/src/subghz/rf_frequency.rs
View File

@ -89,10 +89,7 @@ impl RfFreq {
// Get the frequency bit value.
const fn as_bits(&self) -> u32 {
((self.buf[1] as u32) << 24)
| ((self.buf[2] as u32) << 16)
| ((self.buf[3] as u32) << 8)
| (self.buf[4] as u32)
((self.buf[1] as u32) << 24) | ((self.buf[2] as u32) << 16) | ((self.buf[3] as u32) << 8) | (self.buf[4] as u32)
}
/// Get the actual frequency.

4
embassy-stm32/src/subghz/sleep_cfg.rs
View File

@ -49,9 +49,7 @@ impl SleepCfg {
/// # assert_eq!(u8::from(SLEEP_CFG), 0b101);
/// ```
pub const fn new() -> SleepCfg {
SleepCfg(0)
.set_startup(Startup::Warm)
.set_rtc_wakeup_en(true)
SleepCfg(0).set_startup(Startup::Warm).set_rtc_wakeup_en(true)
}
/// Set the startup mode.

7
embassy-stm32/src/subghz/status.rs
View File

@ -192,11 +192,6 @@ impl core::fmt::Display for Status {
#[cfg(feature = "defmt")]
impl defmt::Format for Status {
fn format(&self, fmt: defmt::Formatter) {
defmt::write!(
fmt,
"Status {{ mode: {}, cmd: {} }}",
self.mode(),
self.cmd()
)
defmt::write!(fmt, "Status {{ mode: {}, cmd: {} }}", self.mode(), self.cmd())
}
}

16
embassy-stm32/src/subghz/timeout.rs
View File

@ -145,8 +145,7 @@ impl Timeout {
// `core::Duration` were not `const fn`, which leads to the hacks
// you see here.
let nanos: u128 = duration.as_nanos();
const UPPER_LIMIT: u128 =
Timeout::MAX.as_nanos() as u128 + (Timeout::RESOLUTION_NANOS as u128) / 2;
const UPPER_LIMIT: u128 = Timeout::MAX.as_nanos() as u128 + (Timeout::RESOLUTION_NANOS as u128) / 2;
const LOWER_LIMIT: u128 = (((Timeout::RESOLUTION_NANOS as u128) + 1) / 2) as u128;
if nanos > UPPER_LIMIT {
@ -420,15 +419,13 @@ impl From<Timeout> for embassy::time::Duration {
#[cfg(test)]
mod tests {
use super::{Timeout, ValueError};
use core::time::Duration;
use super::{Timeout, ValueError};
#[test]
fn saturate() {
assert_eq!(
Timeout::from_duration_sat(Duration::from_secs(u64::MAX)),
Timeout::MAX
);
assert_eq!(Timeout::from_duration_sat(Duration::from_secs(u64::MAX)), Timeout::MAX);
}
#[test]
@ -455,10 +452,7 @@ mod tests {
#[test]
fn upper_limit() {
let high: Duration = Timeout::MAX.as_duration() + Timeout::RESOLUTION / 2;
assert_eq!(
Timeout::from_duration(high),
Ok(Timeout::from_raw(0xFFFFFF))
);
assert_eq!(Timeout::from_duration(high), Ok(Timeout::from_raw(0xFFFFFF)));
let too_high: Duration = high + Duration::from_nanos(1);
assert_eq!(

28
embassy-stm32/src/time_driver.rs
View File

@ -1,22 +1,20 @@
use crate::interrupt::InterruptExt;
use atomic_polyfill::{AtomicU32, AtomicU8};
use core::cell::Cell;
use core::convert::TryInto;
use core::sync::atomic::{compiler_fence, Ordering};
use core::{mem, ptr};
use atomic_polyfill::{AtomicU32, AtomicU8};
use embassy::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy::blocking_mutex::Mutex;
use embassy::time::driver::{AlarmHandle, Driver};
use embassy::time::TICKS_PER_SECOND;
use stm32_metapac::timer::regs;
use crate::interrupt;
use crate::interrupt::CriticalSection;
use crate::interrupt::{CriticalSection, InterruptExt};
use crate::pac::timer::vals;
use crate::peripherals;
use crate::rcc::sealed::RccPeripheral;
use crate::timer::sealed::Basic16bitInstance as BasicInstance;
use crate::timer::sealed::GeneralPurpose16bitInstance as Instance;
use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance};
use crate::{interrupt, peripherals};
#[cfg(not(any(time_driver_tim12, time_driver_tim15)))]
const ALARM_COUNT: usize = 3;
@ -271,15 +269,13 @@ impl Driver for RtcDriver {
}
unsafe fn allocate_alarm(&self) -> Option<AlarmHandle> {
let id = self
.alarm_count
.fetch_update(Ordering::AcqRel, Ordering::Acquire, |x| {
if x < ALARM_COUNT as u8 {
Some(x + 1)
} else {
None
}
});
let id = self.alarm_count.fetch_update(Ordering::AcqRel, Ordering::Acquire, |x| {
if x < ALARM_COUNT as u8 {
Some(x + 1)
} else {
None
}
});
match id {
Ok(id) => Some(AlarmHandle::new(id)),

15
embassy-stm32/src/timer/mod.rs
View File

@ -1,9 +1,10 @@
use crate::interrupt::Interrupt;
use crate::rcc::{sealed::RccPeripheral as __RccPeri, RccPeripheral};
use crate::time::Hertz;
use stm32_metapac::timer::vals;
use crate::interrupt::Interrupt;
use crate::rcc::sealed::RccPeripheral as __RccPeri;
use crate::rcc::RccPeripheral;
use crate::time::Hertz;
#[cfg(feature = "unstable-pac")]
pub mod low_level {
pub use super::sealed::*;
@ -86,8 +87,7 @@ macro_rules! impl_basic_16bit_timer {
let timer_f = Self::frequency().0;
let pclk_ticks_per_timer_period = timer_f / f;
let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 16)).try_into());
let arr: u16 =
unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into());
let arr: u16 = unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into());
let regs = Self::regs();
unsafe {
@ -138,8 +138,7 @@ macro_rules! impl_32bit_timer {
let timer_f = Self::frequency().0;
let pclk_ticks_per_timer_period = (timer_f / f) as u64;
let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 32)).try_into());
let arr: u32 =
unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into()));
let arr: u32 = unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into()));
let regs = Self::regs_gp32();
unsafe {

3
embassy-stm32/src/usart/buffered.rs
View File

@ -1,6 +1,7 @@
use atomic_polyfill::{compiler_fence, Ordering};
use core::future::Future;
use core::task::Poll;
use atomic_polyfill::{compiler_fence, Ordering};
use embassy::waitqueue::WakerRegistration;
use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
use embassy_hal_common::ring_buffer::RingBuffer;

18
embassy-stm32/src/usart/mod.rs
View File

@ -1,15 +1,15 @@
#![macro_use]
use crate::interrupt::Interrupt;
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use crate::dma::NoDma;
use crate::gpio::sealed::AFType;
use crate::interrupt::Interrupt;
use crate::pac::usart::{regs, vals};
use crate::peripherals;
use crate::rcc::RccPeripheral;
use crate::{peripherals, Unborrow};
#[derive(Clone, Copy, PartialEq, Eq, Debug)]
pub enum DataBits {
@ -314,18 +314,14 @@ mod eh02 {
}
}
impl<'d, T: Instance, TxDma, RxDma> embedded_hal_02::serial::Read<u8>
for Uart<'d, T, TxDma, RxDma>
{
impl<'d, T: Instance, TxDma, RxDma> embedded_hal_02::serial::Read<u8> for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
embedded_hal_02::serial::Read::read(&mut self.rx)
}
}
impl<'d, T: Instance, TxDma, RxDma> embedded_hal_02::blocking::serial::Write<u8>
for Uart<'d, T, TxDma, RxDma>
{
impl<'d, T: Instance, TxDma, RxDma> embedded_hal_02::blocking::serial::Write<u8> for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(buffer)
@ -351,9 +347,7 @@ mod eh1 {
}
}
impl<'d, T: Instance, TxDma, RxDma> embedded_hal_1::serial::ErrorType
for Uart<'d, T, TxDma, RxDma>
{
impl<'d, T: Instance, TxDma, RxDma> embedded_hal_1::serial::ErrorType for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
}

1
embassy-stm32/src/usb/mod.rs
View File

@ -1,5 +1,4 @@
use crate::interrupt::Interrupt;
use crate::rcc::RccPeripheral;
#[cfg(feature = "nightly")]

28
embassy-stm32/src/usb/usb.rs
View File

@ -1,11 +1,10 @@
#![macro_use]
use crate::interrupt::InterruptExt;
use crate::Unborrow;
use atomic_polyfill::{AtomicBool, AtomicU8};
use core::marker::PhantomData;
use core::sync::atomic::Ordering;
use core::task::Poll;
use atomic_polyfill::{AtomicBool, AtomicU8};
use embassy::time::{block_for, Duration};
use embassy::waitqueue::AtomicWaker;
use embassy_hal_common::unborrow;
@ -16,12 +15,12 @@ use futures::Future;
use pac::common::{Reg, RW};
use pac::usb::vals::{EpType, Stat};
use super::{DmPin, DpPin, Instance};
use crate::gpio::sealed::AFType;
use crate::pac;
use crate::interrupt::InterruptExt;
use crate::pac::usb::regs;
use crate::rcc::sealed::RccPeripheral;
use super::{DmPin, DpPin, Instance};
use crate::{pac, Unborrow};
const EP_COUNT: usize = 8;
@ -105,11 +104,7 @@ impl<T: Instance> EndpointBuffer<T> {
if i * 2 + 1 < buf.len() {
val |= (buf[i * 2 + 1] as u16) << 8;
}
unsafe {
T::regs()
.ep_mem(self.addr as usize / 2 + i)
.write_value(val)
};
unsafe { T::regs().ep_mem(self.addr as usize / 2 + i).write_value(val) };
}
}
}
@ -146,9 +141,7 @@ impl<'d, T: Instance> Driver<'d, T> {
unsafe {
crate::peripherals::PWR::enable();
pac::PWR
.cr2()
.modify(|w| w.set_usv(pac::pwr::vals::Usv::VALID));
pac::PWR.cr2().modify(|w| w.set_usv(pac::pwr::vals::Usv::VALID));
}
unsafe {
@ -857,12 +850,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
}
}
fn data_out<'a>(
&'a mut self,
buf: &'a mut [u8],
first: bool,
last: bool,
) -> Self::DataOutFuture<'a> {
fn data_out<'a>(&'a mut self, buf: &'a mut [u8], first: bool, last: bool) -> Self::DataOutFuture<'a> {
async move {
let regs = T::regs();

9
embassy-stm32/src/usb_otg.rs
View File

@ -1,9 +1,10 @@
use crate::Unborrow;
use core::marker::PhantomData;
use embassy_hal_common::unborrow;
use crate::gpio::sealed::AFType;
use crate::{peripherals, rcc::RccPeripheral};
use crate::rcc::RccPeripheral;
use crate::{peripherals, Unborrow};
macro_rules! config_ulpi_pins {
($($pin:ident),*) => {
@ -76,8 +77,8 @@ impl<'d, T: Instance> UsbOtg<'d, T> {
ulpi_d7: impl Unborrow<Target = impl UlpiD7Pin<T>> + 'd,
) -> Self {
config_ulpi_pins!(
ulpi_clk, ulpi_dir, ulpi_nxt, ulpi_stp, ulpi_d0, ulpi_d1, ulpi_d2, ulpi_d3, ulpi_d4,
ulpi_d5, ulpi_d6, ulpi_d7
ulpi_clk, ulpi_dir, ulpi_nxt, ulpi_stp, ulpi_d0, ulpi_d1, ulpi_d2, ulpi_d3, ulpi_d4, ulpi_d5, ulpi_d6,
ulpi_d7
);
Self {