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@ -20,18 +20,12 @@ pub struct Config {
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pub pll48: bool,
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}
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unsafe fn setup_pll(
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pllsrcclk: u32,
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use_hse: bool,
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pllsysclk: Option<u32>,
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pll48clk: bool,
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) -> PllResults {
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unsafe fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
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use crate::pac::rcc::vals::{Pllp, Pllsrc};
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let sysclk = pllsysclk.unwrap_or(pllsrcclk);
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if pllsysclk.is_none() && !pll48clk {
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RCC.pllcfgr()
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.modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
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RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
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return PllResults {
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use_pll: false,
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@ -47,11 +41,7 @@ unsafe fn setup_pll(
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// Sysclk output divisor must be one of 2, 4, 6 or 8
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let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
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let target_freq = if pll48clk {
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48_000_000
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} else {
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sysclk * sysclk_div
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};
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let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
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// Find the lowest pllm value that minimize the difference between
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// target frequency and the real vco_out frequency.
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@ -135,11 +125,7 @@ pub(crate) unsafe fn init(config: Config) {
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assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
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}
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let sysclk = if sysclk_on_pll {
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unwrap!(plls.pllsysclk)
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} else {
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sysclk
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};
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let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
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// AHB prescaler
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let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
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@ -269,9 +255,7 @@ mod max {
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pub(crate) const SYSCLK_MAX: u32 = 168_000_000;
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#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
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pub(crate) const SYSCLK_MAX: u32 = 100_000_000;
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#[cfg(any(
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stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,
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))]
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
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pub(crate) const SYSCLK_MAX: u32 = 180_000_000;
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pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 168_000_000;
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