From 1cc61dc68a64398159214018296c6a6141e760c5 Mon Sep 17 00:00:00 2001 From: Marco Pastrello Date: Thu, 4 May 2023 21:32:37 +0200 Subject: [PATCH 1/5] Support PLLXTPRE switch. See figure 2. Clock tree page 12 DS5319 Rev 18 https://www.st.com/resource/en/datasheet/stm32f103cb.pdf --- embassy-stm32/src/rcc/f1.rs | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs index e667dbf9..1c14429f 100644 --- a/embassy-stm32/src/rcc/f1.rs +++ b/embassy-stm32/src/rcc/f1.rs @@ -24,10 +24,15 @@ pub struct Config { pub pclk1: Option, pub pclk2: Option, pub adcclk: Option, + pub pllxtpre: Option, } pub(crate) unsafe fn init(config: Config) { - let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0 / 2); + let pllsrcclk = config.hse.map(|hse| hse.0 / match config.pllxtpre { + Some(b) => if b {2} else {1}, + None => {1}, + }).unwrap_or(HSI_FREQ.0 / 2); + let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk); let pllmul = sysclk / pllsrcclk; @@ -143,6 +148,7 @@ pub(crate) unsafe fn init(config: Config) { } if let Some(pllmul_bits) = pllmul_bits { + RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(config.pllxtpre.is_some() as u8))); // enable PLL and wait for it to be ready RCC.cfgr().modify(|w| { w.set_pllmul(Pllmul(pllmul_bits)); From 5158014f3f77b20db34dd398633fc26e8e7d2e60 Mon Sep 17 00:00:00 2001 From: Marco Pastrello Date: Thu, 4 May 2023 22:59:52 +0200 Subject: [PATCH 2/5] PPLXTPRE is a bool. This flag for example permits the following clock tree configuration on stm32f103r8 let mut config = Config::default(); config.rcc.hse = Some(Hertz(16_000_000)); config.rcc.sys_ck = Some(Hertz(72_000_000)); config.rcc.pclk1 = Some(Hertz(36_000_000)); config.rcc.pclk2 = Some(Hertz(72_000_000)); config.rcc.pllxtpre = true; Init fails if pllxtpre is false. --- embassy-stm32/src/rcc/f1.rs | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs index 1c14429f..620638ab 100644 --- a/embassy-stm32/src/rcc/f1.rs +++ b/embassy-stm32/src/rcc/f1.rs @@ -24,14 +24,11 @@ pub struct Config { pub pclk1: Option, pub pclk2: Option, pub adcclk: Option, - pub pllxtpre: Option, + pub pllxtpre: bool, } pub(crate) unsafe fn init(config: Config) { - let pllsrcclk = config.hse.map(|hse| hse.0 / match config.pllxtpre { - Some(b) => if b {2} else {1}, - None => {1}, - }).unwrap_or(HSI_FREQ.0 / 2); + let pllsrcclk = config.hse.map(|hse| hse.0 / if config.pllxtpre {2} else {1}).unwrap_or(HSI_FREQ.0 / 2); let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk); let pllmul = sysclk / pllsrcclk; @@ -148,7 +145,7 @@ pub(crate) unsafe fn init(config: Config) { } if let Some(pllmul_bits) = pllmul_bits { - RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(config.pllxtpre.is_some() as u8))); + RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(if config.pllxtpre {1u8} else {0u8}))); // enable PLL and wait for it to be ready RCC.cfgr().modify(|w| { w.set_pllmul(Pllmul(pllmul_bits)); From 2dcbe75cca84cc44fc2357091aec20d2d9d5be00 Mon Sep 17 00:00:00 2001 From: Marco Pastrello Date: Thu, 4 May 2023 23:51:42 +0200 Subject: [PATCH 3/5] beautify --- embassy-stm32/src/rcc/f1.rs | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs index 620638ab..106acb09 100644 --- a/embassy-stm32/src/rcc/f1.rs +++ b/embassy-stm32/src/rcc/f1.rs @@ -28,7 +28,10 @@ pub struct Config { } pub(crate) unsafe fn init(config: Config) { - let pllsrcclk = config.hse.map(|hse| hse.0 / if config.pllxtpre {2} else {1}).unwrap_or(HSI_FREQ.0 / 2); + let pllsrcclk = config + .hse + .map(|hse| if config.pllxtpre { hse.0 / 2 } else { hse.0 }) + .unwrap_or(HSI_FREQ.0 / 2); let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk); let pllmul = sysclk / pllsrcclk; @@ -145,7 +148,11 @@ pub(crate) unsafe fn init(config: Config) { } if let Some(pllmul_bits) = pllmul_bits { - RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(if config.pllxtpre {1u8} else {0u8}))); + { + let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 }; + RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag))); + } + // enable PLL and wait for it to be ready RCC.cfgr().modify(|w| { w.set_pllmul(Pllmul(pllmul_bits)); From c37f86ff1c507cc036b9754a00dea85d439a8369 Mon Sep 17 00:00:00 2001 From: Marco Pastrello Date: Fri, 5 May 2023 00:12:32 +0200 Subject: [PATCH 4/5] removes unecessary braces --- embassy-stm32/src/rcc/f1.rs | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs index 106acb09..3c374adf 100644 --- a/embassy-stm32/src/rcc/f1.rs +++ b/embassy-stm32/src/rcc/f1.rs @@ -148,10 +148,8 @@ pub(crate) unsafe fn init(config: Config) { } if let Some(pllmul_bits) = pllmul_bits { - { - let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 }; - RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag))); - } + let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 }; + RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag))); // enable PLL and wait for it to be ready RCC.cfgr().modify(|w| { From db2bc8783e756d0e10838869603c844d8c276feb Mon Sep 17 00:00:00 2001 From: Marco Pastrello Date: Fri, 5 May 2023 19:04:58 +0200 Subject: [PATCH 5/5] Improve readability --- embassy-stm32/src/rcc/f1.rs | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs index 3c374adf..4769b705 100644 --- a/embassy-stm32/src/rcc/f1.rs +++ b/embassy-stm32/src/rcc/f1.rs @@ -28,10 +28,8 @@ pub struct Config { } pub(crate) unsafe fn init(config: Config) { - let pllsrcclk = config - .hse - .map(|hse| if config.pllxtpre { hse.0 / 2 } else { hse.0 }) - .unwrap_or(HSI_FREQ.0 / 2); + let pllxtpre_div = if config.pllxtpre { 2 } else { 1 }; + let pllsrcclk = config.hse.map(|hse| hse.0 / pllxtpre_div).unwrap_or(HSI_FREQ.0 / 2); let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk); let pllmul = sysclk / pllsrcclk;