parent
c28a6bdd0b
commit
aa2fa29b89
@ -50,7 +50,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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while T::regs().cr().read().adcal() {}
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// Wait more than 4 clock cycles after adcal is cleared (RM0364 p. 223)
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delay.delay_us(6 * 1_000_000 / Self::freq().0);
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delay.delay_us(1 + (6 * 1_000_000 / Self::freq().0));
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// Enable the adc
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T::regs().cr().modify(|w| w.set_aden(true));
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