it's alive
This commit is contained in:
Dario Nieuwenhuis
@ -11,31 +11,28 @@ defmt-info = [ ]
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defmt-warn = [ ]
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defmt-error = [ ]
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stm32f401 = ["stm32f4xx-hal/stm32f401"]
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stm32f405 = ["stm32f4xx-hal/stm32f405"]
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stm32f407 = ["stm32f4xx-hal/stm32f407"]
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stm32f410 = ["stm32f4xx-hal/stm32f410"]
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stm32f411 = ["stm32f4xx-hal/stm32f411"]
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stm32f412 = ["stm32f4xx-hal/stm32f412"]
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stm32f413 = ["stm32f4xx-hal/stm32f413"]
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stm32f415 = ["stm32f4xx-hal/stm32f405"]
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stm32f417 = ["stm32f4xx-hal/stm32f407"]
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stm32f423 = ["stm32f4xx-hal/stm32f413"]
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stm32f427 = ["stm32f4xx-hal/stm32f427"]
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stm32f429 = ["stm32f4xx-hal/stm32f429"]
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stm32f437 = ["stm32f4xx-hal/stm32f427"]
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stm32f439 = ["stm32f4xx-hal/stm32f429"]
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stm32f446 = ["stm32f4xx-hal/stm32f446"]
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stm32f469 = ["stm32f4xx-hal/stm32f469"]
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stm32f479 = ["stm32f4xx-hal/stm32f469"]
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stm32l0x1 = ["stm32l0xx-hal/stm32l0x1"]
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stm32l0x2 = ["stm32l0xx-hal/stm32l0x2"]
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stm32l0x3 = ["stm32l0xx-hal/stm32l0x3"]
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f4 = []
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f401 = ["f4"]
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f405 = ["f4"]
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f407 = ["f4"]
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f410 = ["f4"]
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f411 = ["f4"]
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f412 = ["f4"]
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f413 = ["f4"]
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f415 = ["f4"]
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f417 = ["f4"]
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f423 = ["f4"]
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f427 = ["f4"]
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f429 = ["f4"]
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f437 = ["f4"]
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f439 = ["f4"]
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f446 = ["f4"]
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f469 = ["f4"]
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f479 = ["f4"]
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[dependencies]
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embassy = { version = "0.1.0", path = "../embassy" }
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embassy-macros = { version = "0.1.0", path = "../embassy-macros", features = ["stm32"]}
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embassy-macros = { version = "0.1.0", path = "../embassy-macros" }
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embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
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defmt = { version = "0.2.0", optional = true }
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@ -43,9 +40,5 @@ log = { version = "0.4.11", optional = true }
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cortex-m-rt = "0.6.13"
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cortex-m = "0.7.1"
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embedded-hal = { version = "0.2.4" }
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embedded-dma = { version = "0.1.2" }
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bxcan = "0.5.0"
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nb = "*"
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stm32f4xx-hal = { version = "0.9.0", features = ["rt", "can", "usb_fs"], optional = true }
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stm32l0xx-hal = { version = "0.7.0", features = ["rt"], optional = true }
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futures = { version = "0.3.5", default-features = false, features = ["async-await"] }
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futures = { version = "0.3.5", default-features = false, features = ["async-await"] }
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stm32-metapac = { path = "../../stm32-metapac"}
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6
embassy-stm32/src/chip/f429.rs
Normal file
6
embassy-stm32/src/chip/f429.rs
Normal file
@ -0,0 +1,6 @@
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use embassy_extras::peripherals;
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peripherals!(
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PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
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PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15,
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);
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370
embassy-stm32/src/gpio.rs
Normal file
370
embassy-stm32/src/gpio.rs
Normal file
@ -0,0 +1,370 @@
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use core::convert::Infallible;
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use core::hint::unreachable_unchecked;
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use core::marker::PhantomData;
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use embassy::util::PeripheralBorrow;
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use embassy_extras::{impl_unborrow, unborrow};
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use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin};
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use gpio::vals::{self, Pupdr};
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use crate::pac;
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use crate::pac::gpio_v2 as gpio;
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use crate::peripherals;
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/// A GPIO port with up to 16 pins.
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#[derive(Debug, Eq, PartialEq)]
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pub enum Port {
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PortA,
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PortB,
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}
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/// Pull setting for an input.
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#[derive(Debug, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Pull {
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None,
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Up,
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Down,
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}
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/*
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/// GPIO input driver.
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pub struct Input<'d, T: Pin> {
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pub(crate) pin: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Pin> Input<'d, T> {
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pub fn new(pin: impl PeripheralBorrow<Target = T> + 'd, pull: Pull) -> Self {
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unborrow!(pin);
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pin.conf().write(|w| {
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w.dir().input();
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w.input().connect();
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match pull {
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Pull::None => {
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w.pull().disabled();
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}
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Pull::Up => {
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w.pull().pullup();
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}
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Pull::Down => {
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w.pull().pulldown();
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}
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}
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w.drive().s0s1();
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w.sense().disabled();
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w
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});
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Self {
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pin,
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Pin> Drop for Input<'d, T> {
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fn drop(&mut self) {
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self.pin.conf().reset();
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}
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}
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impl<'d, T: Pin> InputPin for Input<'d, T> {
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type Error = Infallible;
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fn is_high(&self) -> Result<bool, Self::Error> {
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self.is_low().map(|v| !v)
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.block().in_.read().bits() & (1 << self.pin.pin()) == 0)
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}
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}
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*/
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/// Digital input or output level.
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#[derive(Debug, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Level {
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Low,
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High,
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}
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/// GPIO output driver.
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pub struct Output<'d, T: Pin> {
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pub(crate) pin: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Pin> Output<'d, T> {
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pub fn new(pin: impl PeripheralBorrow<Target = T> + 'd, initial_output: Level) -> Self {
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unborrow!(pin);
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match initial_output {
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Level::High => pin.set_high(),
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Level::Low => pin.set_low(),
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}
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cortex_m::interrupt::free(|_| unsafe {
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let r = pin.block();
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let n = pin.pin() as usize;
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r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
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r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
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r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
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});
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Self {
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pin,
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Pin> Drop for Output<'d, T> {
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fn drop(&mut self) {
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cortex_m::interrupt::free(|_| unsafe {
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let r = self.pin.block();
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let n = self.pin.pin() as usize;
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r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
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});
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}
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}
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impl<'d, T: Pin> OutputPin for Output<'d, T> {
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type Error = Infallible;
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/// Set the output as high.
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fn set_high(&mut self) -> Result<(), Self::Error> {
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self.pin.set_high();
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Ok(())
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}
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/// Set the output as low.
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fn set_low(&mut self) -> Result<(), Self::Error> {
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self.pin.set_low();
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Ok(())
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}
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}
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impl<'d, T: Pin> StatefulOutputPin for Output<'d, T> {
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/// Is the output pin set as high?
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fn is_set_high(&self) -> Result<bool, Self::Error> {
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self.is_set_low().map(|v| !v)
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}
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/// Is the output pin set as low?
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fn is_set_low(&self) -> Result<bool, Self::Error> {
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let state = unsafe { self.pin.block().odr().read().odr(self.pin.pin() as _) };
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Ok(state == vals::Odr::LOW)
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}
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}
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pub(crate) mod sealed {
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use super::*;
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pub trait Pin {
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fn pin_port(&self) -> u8;
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#[inline]
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fn _pin(&self) -> u8 {
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self.pin_port() % 16
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}
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#[inline]
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fn _port(&self) -> u8 {
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self.pin_port() / 16
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}
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#[inline]
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fn block(&self) -> gpio::Gpio {
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let p = 0x4002_0000 + (self._port() as u32) * 0x400;
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gpio::Gpio(p as *mut u8)
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}
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/// Set the output as high.
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#[inline]
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fn set_high(&self) {
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unsafe {
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self.block()
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.bsrr()
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.write(|w| w.set_bs(self._pin() as _, true));
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}
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}
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/// Set the output as low.
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#[inline]
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fn set_low(&self) {
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unsafe {
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self.block()
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.bsrr()
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.write(|w| w.set_br(self._pin() as _, true));
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}
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}
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}
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pub trait OptionalPin {}
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}
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pub trait Pin: sealed::Pin + Sized {
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/// Number of the pin within the port (0..31)
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#[inline]
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fn pin(&self) -> u8 {
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self._pin()
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}
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/// Port of the pin
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#[inline]
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fn port(&self) -> Port {
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match self.pin_port() / 16 {
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0 => Port::PortA,
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1 => Port::PortB,
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_ => unsafe { unreachable_unchecked() },
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}
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}
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#[inline]
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fn psel_bits(&self) -> u32 {
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self.pin_port() as u32
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}
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/// Convert from concrete pin type PX_XX to type erased `AnyPin`.
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#[inline]
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fn degrade(self) -> AnyPin {
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AnyPin {
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pin_port: self.pin_port(),
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}
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}
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}
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// Type-erased GPIO pin
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pub struct AnyPin {
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pin_port: u8,
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}
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impl AnyPin {
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#[inline]
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pub unsafe fn steal(pin_port: u8) -> Self {
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Self { pin_port }
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}
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}
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impl_unborrow!(AnyPin);
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impl Pin for AnyPin {}
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impl sealed::Pin for AnyPin {
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#[inline]
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fn pin_port(&self) -> u8 {
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self.pin_port
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}
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}
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// ====================
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pub trait OptionalPin: sealed::OptionalPin + Sized {
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type Pin: Pin;
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fn pin(&self) -> Option<&Self::Pin>;
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fn pin_mut(&mut self) -> Option<&mut Self::Pin>;
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#[inline]
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fn psel_bits(&self) -> u32 {
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self.pin().map_or(1u32 << 31, |pin| Pin::psel_bits(pin))
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}
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|
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/// Convert from concrete pin type PX_XX to type erased `Option<AnyPin>`.
|
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#[inline]
|
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fn degrade_optional(mut self) -> Option<AnyPin> {
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self.pin_mut()
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.map(|pin| unsafe { core::ptr::read(pin) }.degrade())
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}
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}
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impl<T: Pin> sealed::OptionalPin for T {}
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impl<T: Pin> OptionalPin for T {
|
||||
type Pin = T;
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|
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#[inline]
|
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fn pin(&self) -> Option<&T> {
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Some(self)
|
||||
}
|
||||
|
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#[inline]
|
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fn pin_mut(&mut self) -> Option<&mut T> {
|
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Some(self)
|
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}
|
||||
}
|
||||
|
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// Uninhabited enum, so it's actually impossible to create a DummyPin value.
|
||||
#[doc(hidden)]
|
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pub enum DummyPin {}
|
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impl Pin for DummyPin {}
|
||||
impl sealed::Pin for DummyPin {
|
||||
#[inline]
|
||||
fn pin_port(&self) -> u8 {
|
||||
unreachable!()
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct NoPin;
|
||||
impl_unborrow!(NoPin);
|
||||
impl sealed::OptionalPin for NoPin {}
|
||||
impl OptionalPin for NoPin {
|
||||
type Pin = DummyPin;
|
||||
|
||||
#[inline]
|
||||
fn pin(&self) -> Option<&DummyPin> {
|
||||
None
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn pin_mut(&mut self) -> Option<&mut DummyPin> {
|
||||
None
|
||||
}
|
||||
}
|
||||
|
||||
// ====================
|
||||
|
||||
macro_rules! impl_pin {
|
||||
($type:ident, $port_num:expr, $pin_num:expr) => {
|
||||
impl Pin for peripherals::$type {}
|
||||
impl sealed::Pin for peripherals::$type {
|
||||
#[inline]
|
||||
fn pin_port(&self) -> u8 {
|
||||
$port_num * 16 + $pin_num
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
impl_pin!(PA0, 0, 0);
|
||||
impl_pin!(PA1, 0, 1);
|
||||
impl_pin!(PA2, 0, 2);
|
||||
impl_pin!(PA3, 0, 3);
|
||||
impl_pin!(PA4, 0, 4);
|
||||
impl_pin!(PA5, 0, 5);
|
||||
impl_pin!(PA6, 0, 6);
|
||||
impl_pin!(PA7, 0, 7);
|
||||
impl_pin!(PA8, 0, 8);
|
||||
impl_pin!(PA9, 0, 9);
|
||||
impl_pin!(PA10, 0, 10);
|
||||
impl_pin!(PA11, 0, 11);
|
||||
impl_pin!(PA12, 0, 12);
|
||||
impl_pin!(PA13, 0, 13);
|
||||
impl_pin!(PA14, 0, 14);
|
||||
impl_pin!(PA15, 0, 15);
|
||||
impl_pin!(PB0, 1, 0);
|
||||
impl_pin!(PB1, 1, 1);
|
||||
impl_pin!(PB2, 1, 2);
|
||||
impl_pin!(PB3, 1, 3);
|
||||
impl_pin!(PB4, 1, 4);
|
||||
impl_pin!(PB5, 1, 5);
|
||||
impl_pin!(PB6, 1, 6);
|
||||
impl_pin!(PB7, 1, 7);
|
||||
impl_pin!(PB8, 1, 8);
|
||||
impl_pin!(PB9, 1, 9);
|
||||
impl_pin!(PB10, 1, 10);
|
||||
impl_pin!(PB11, 1, 11);
|
||||
impl_pin!(PB12, 1, 12);
|
||||
impl_pin!(PB13, 1, 13);
|
||||
impl_pin!(PB14, 1, 14);
|
||||
impl_pin!(PB15, 1, 15);
|
||||
@ -6,395 +6,30 @@
|
||||
#![feature(type_alias_impl_trait)]
|
||||
#![allow(incomplete_features)]
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
mod f4;
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
pub use {stm32f4xx_hal as hal, stm32f4xx_hal::stm32 as pac};
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
pub use {stm32l0xx_hal as hal, stm32l0xx_hal::pac};
|
||||
|
||||
pub mod fmt;
|
||||
|
||||
pub mod exti;
|
||||
pub mod interrupt;
|
||||
#[cfg_attr(feature = "f401", path = "chip/f401.rs")]
|
||||
#[cfg_attr(feature = "f405", path = "chip/f405.rs")]
|
||||
#[cfg_attr(feature = "f407", path = "chip/f407.rs")]
|
||||
#[cfg_attr(feature = "f410", path = "chip/f410.rs")]
|
||||
#[cfg_attr(feature = "f411", path = "chip/f411.rs")]
|
||||
#[cfg_attr(feature = "f412", path = "chip/f412.rs")]
|
||||
#[cfg_attr(feature = "f413", path = "chip/f413.rs")]
|
||||
#[cfg_attr(feature = "f415", path = "chip/f415.rs")]
|
||||
#[cfg_attr(feature = "f417", path = "chip/f417.rs")]
|
||||
#[cfg_attr(feature = "f423", path = "chip/f423.rs")]
|
||||
#[cfg_attr(feature = "f427", path = "chip/f427.rs")]
|
||||
#[cfg_attr(feature = "f429", path = "chip/f429.rs")]
|
||||
#[cfg_attr(feature = "f437", path = "chip/f437.rs")]
|
||||
#[cfg_attr(feature = "f439", path = "chip/f439.rs")]
|
||||
#[cfg_attr(feature = "f446", path = "chip/f446.rs")]
|
||||
#[cfg_attr(feature = "f469", path = "chip/f469.rs")]
|
||||
#[cfg_attr(feature = "f479", path = "chip/f479.rs")]
|
||||
mod chip;
|
||||
pub use chip::{peripherals, Peripherals};
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
pub mod can;
|
||||
pub mod gpio;
|
||||
//pub mod exti;
|
||||
//pub mod interrupt;
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
pub mod rtc;
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
pub use f4::{serial, spi};
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
unsafe impl embassy_extras::usb::USBInterrupt for interrupt::OTG_FS {}
|
||||
|
||||
use core::option::Option;
|
||||
use hal::prelude::*;
|
||||
use hal::rcc::Clocks;
|
||||
|
||||
#[cfg(feature = "stm32f446")]
|
||||
embassy_extras::std_peripherals! {
|
||||
DCMI,
|
||||
FMC,
|
||||
DBGMCU,
|
||||
DMA2,
|
||||
DMA1,
|
||||
// RCC,
|
||||
GPIOH,
|
||||
GPIOG,
|
||||
GPIOF,
|
||||
GPIOE,
|
||||
GPIOD,
|
||||
GPIOC,
|
||||
GPIOB,
|
||||
GPIOA,
|
||||
SYSCFG,
|
||||
SPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
SPI4,
|
||||
ADC1,
|
||||
ADC2,
|
||||
ADC3,
|
||||
USART6,
|
||||
USART1,
|
||||
USART2,
|
||||
USART3,
|
||||
DAC,
|
||||
I2C3,
|
||||
I2C2,
|
||||
I2C1,
|
||||
IWDG,
|
||||
WWDG,
|
||||
RTC,
|
||||
UART4,
|
||||
UART5,
|
||||
ADC_COMMON,
|
||||
TIM1,
|
||||
TIM2,
|
||||
TIM8,
|
||||
// TIM3,
|
||||
TIM4,
|
||||
TIM5,
|
||||
TIM9,
|
||||
TIM12,
|
||||
TIM10,
|
||||
TIM13,
|
||||
TIM14,
|
||||
TIM11,
|
||||
TIM6,
|
||||
TIM7,
|
||||
CRC,
|
||||
OTG_FS_GLOBAL,
|
||||
OTG_FS_HOST,
|
||||
OTG_FS_DEVICE,
|
||||
OTG_FS_PWRCLK,
|
||||
CAN1,
|
||||
CAN2,
|
||||
FLASH,
|
||||
EXTI,
|
||||
OTG_HS_GLOBAL,
|
||||
OTG_HS_HOST,
|
||||
OTG_HS_DEVICE,
|
||||
OTG_HS_PWRCLK,
|
||||
SAI1,
|
||||
SAI2,
|
||||
PWR,
|
||||
QUADSPI,
|
||||
SPDIFRX,
|
||||
// SDMMC,
|
||||
HDMI_CEC,
|
||||
FPU,
|
||||
STK,
|
||||
NVIC_STIR,
|
||||
FPU_CPACR,
|
||||
SCB_ACTRL,
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f405")]
|
||||
embassy_extras::std_peripherals! {
|
||||
RNG,
|
||||
DCMI,
|
||||
FSMC,
|
||||
DBGMCU,
|
||||
DMA2,
|
||||
DMA1,
|
||||
// RCC,
|
||||
GPIOI,
|
||||
GPIOH,
|
||||
GPIOG,
|
||||
GPIOF,
|
||||
GPIOE,
|
||||
GPIOD,
|
||||
GPIOC,
|
||||
GPIOJ,
|
||||
GPIOK,
|
||||
GPIOB,
|
||||
GPIOA,
|
||||
SYSCFG,
|
||||
SPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
I2S2EXT,
|
||||
I2S3EXT,
|
||||
SPI4,
|
||||
SPI5,
|
||||
SPI6,
|
||||
SDIO,
|
||||
ADC1,
|
||||
ADC2,
|
||||
ADC3,
|
||||
USART6,
|
||||
USART1,
|
||||
USART2,
|
||||
USART3,
|
||||
DAC,
|
||||
PWR,
|
||||
I2C3,
|
||||
I2C2,
|
||||
I2C1,
|
||||
IWDG,
|
||||
WWDG,
|
||||
RTC,
|
||||
UART4,
|
||||
UART5,
|
||||
UART7,
|
||||
UART8,
|
||||
ADC_COMMON,
|
||||
TIM1,
|
||||
TIM8,
|
||||
TIM2,
|
||||
// TIM3,
|
||||
TIM4,
|
||||
TIM5,
|
||||
TIM9,
|
||||
TIM12,
|
||||
TIM10,
|
||||
TIM13,
|
||||
TIM14,
|
||||
TIM11,
|
||||
TIM6,
|
||||
TIM7,
|
||||
ETHERNET_MAC,
|
||||
ETHERNET_MMC,
|
||||
ETHERNET_PTP,
|
||||
ETHERNET_DMA,
|
||||
CRC,
|
||||
OTG_FS_GLOBAL,
|
||||
OTG_FS_HOST,
|
||||
OTG_FS_DEVICE,
|
||||
OTG_FS_PWRCLK,
|
||||
CAN1,
|
||||
CAN2,
|
||||
FLASH,
|
||||
EXTI,
|
||||
OTG_HS_GLOBAL,
|
||||
OTG_HS_HOST,
|
||||
OTG_HS_DEVICE,
|
||||
OTG_HS_PWRCLK,
|
||||
SAI1,
|
||||
LTDC,
|
||||
HASH,
|
||||
CRYP,
|
||||
FPU,
|
||||
STK,
|
||||
NVIC_STIR,
|
||||
FPU_CPACR,
|
||||
SCB_ACTRL,
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f407")]
|
||||
embassy_extras::std_peripherals! {
|
||||
RNG,
|
||||
DCMI,
|
||||
FSMC,
|
||||
DBGMCU,
|
||||
DMA2,
|
||||
DMA1,
|
||||
// RCC,
|
||||
GPIOI,
|
||||
GPIOH,
|
||||
GPIOG,
|
||||
GPIOF,
|
||||
GPIOE,
|
||||
GPIOD,
|
||||
GPIOC,
|
||||
GPIOJ,
|
||||
GPIOK,
|
||||
GPIOB,
|
||||
GPIOA,
|
||||
SYSCFG,
|
||||
SPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
I2S2EXT,
|
||||
I2S3EXT,
|
||||
SPI4,
|
||||
SPI5,
|
||||
SPI6,
|
||||
SDIO,
|
||||
ADC1,
|
||||
ADC2,
|
||||
ADC3,
|
||||
USART6,
|
||||
USART1,
|
||||
USART2,
|
||||
USART3,
|
||||
DAC,
|
||||
PWR,
|
||||
I2C3,
|
||||
I2C2,
|
||||
I2C1,
|
||||
IWDG,
|
||||
WWDG,
|
||||
RTC,
|
||||
UART4,
|
||||
UART5,
|
||||
UART7,
|
||||
UART8,
|
||||
ADC_COMMON,
|
||||
TIM1,
|
||||
TIM8,
|
||||
TIM2,
|
||||
// TIM3,
|
||||
TIM4,
|
||||
TIM5,
|
||||
TIM9,
|
||||
TIM12,
|
||||
TIM10,
|
||||
TIM13,
|
||||
TIM14,
|
||||
TIM11,
|
||||
TIM6,
|
||||
TIM7,
|
||||
ETHERNET_MAC,
|
||||
ETHERNET_MMC,
|
||||
ETHERNET_PTP,
|
||||
ETHERNET_DMA,
|
||||
CRC,
|
||||
OTG_FS_GLOBAL,
|
||||
OTG_FS_HOST,
|
||||
OTG_FS_DEVICE,
|
||||
OTG_FS_PWRCLK,
|
||||
CAN1,
|
||||
CAN2,
|
||||
FLASH,
|
||||
EXTI,
|
||||
OTG_HS_GLOBAL,
|
||||
OTG_HS_HOST,
|
||||
OTG_HS_DEVICE,
|
||||
OTG_HS_PWRCLK,
|
||||
SAI1,
|
||||
LTDC,
|
||||
HASH,
|
||||
CRYP,
|
||||
FPU,
|
||||
STK,
|
||||
NVIC_STIR,
|
||||
FPU_CPACR,
|
||||
SCB_ACTRL,
|
||||
}
|
||||
pub(crate) use stm32_metapac as pac;
|
||||
|
||||
Reference in New Issue
Block a user