diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index e5ba746e..1f170887 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -456,13 +456,14 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::REGS.cr1().modify(|w| {
                 w.set_spe(false);
             });
-            set_rxdmaen(T::REGS, true);
         }
 
         // SPIv3 clears rxfifo on SPE=0
         #[cfg(not(any(spi_v3, spi_v4)))]
         flush_rx_fifo(T::REGS);
 
+        set_rxdmaen(T::REGS, true);
+
         let clock_byte_count = data.len();
 
         let rx_request = self.rxdma.request();
@@ -510,13 +511,14 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::REGS.cr1().modify(|w| {
                 w.set_spe(false);
             });
-            set_rxdmaen(T::REGS, true);
         }
 
         // SPIv3 clears rxfifo on SPE=0
         #[cfg(not(any(spi_v3, spi_v4)))]
         flush_rx_fifo(T::REGS);
 
+        set_rxdmaen(T::REGS, true);
+
         let rx_request = self.rxdma.request();
         let rx_src = T::REGS.rx_ptr();
         unsafe { self.rxdma.start_read(rx_request, rx_src, read, Default::default()) };